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make examples/test_doublepin.sch compile with no errors with ngspice, ghdl and iverilog, this is a test schematic to validate pass-through symbols

This commit is contained in:
Stefan Frederik 2022-10-11 14:25:58 +02:00
parent 3f627123b2
commit ce75ca2bbf
4 changed files with 29 additions and 9 deletions
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4
xschem_library/examples/doublepin.sch
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@ -16,3 +16,7 @@ C {noconn.sym} 210 -260 2 0 {name=l3}
C {noconn.sym} 210 -220 2 0 {name=l4} C {noconn.sym} 210 -220 2 0 {name=l4}
C {noconn.sym} 210 -190 2 0 {name=l5} C {noconn.sym} 210 -190 2 0 {name=l5}
C {noconn.sym} 520 -240 2 1 {name=l6} C {noconn.sym} 520 -240 2 1 {name=l6}
C {use.sym} 380 -480 0 0 {------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;}

28
xschem_library/examples/test_doublepin.sch
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@ -4,11 +4,17 @@ G {}
K {} K {}
V { V {
} }
S {va a 0 pwl 0 0 100n 0 101n 3 S {
vvcc vcc 0 dc 3 .param VCC=2
vvss vss 0 dc 0 vaa3 aa[3] 0 dc 0
vaa2 aa[2] 0 dc 0
.tran 1n 200n} vaa1 aa[1] 0 dc 0
vaa0 aa[0] 0 dc 0
vbb bb 0 dc 0
vcckk cckk 0 dc 0
vrrsstt rrsstt 0 dc 0
.op
}
E {} E {}
T {Netlister allows duplicated pins on symbols T {Netlister allows duplicated pins on symbols
Electrical nodes are propagated through duplicated symbol pins} 50 -1570 0 0 1 1 {} Electrical nodes are propagated through duplicated symbol pins} 50 -1570 0 0 1 1 {}
@ -292,10 +298,10 @@ C {lab_pin.sym} 180 -720 0 0 {name=l31 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 180 -700 0 0 {name=l32 sig_type=std_logic lab=CCKK} C {lab_pin.sym} 180 -700 0 0 {name=l32 sig_type=std_logic lab=CCKK}
C {doublepin.sym} 330 -670 0 0 {name=x7 C {doublepin.sym} 330 -670 0 0 {name=x7
net_name=true} net_name=true}
C {ipin.sym} 100 -80 0 0 { name=p9 lab=RRSSTT } C {iopin.sym} 100 -80 0 0 { name=p9 lab=RRSSTT }
C {ipin.sym} 100 -100 0 0 { name=p10 lab=CCKK } C {iopin.sym} 100 -100 0 0 { name=p10 lab=CCKK }
C {ipin.sym} 100 -120 0 0 { name=p11 lab=BB } C {iopin.sym} 100 -120 0 0 { name=p11 lab=BB }
C {ipin.sym} 100 -140 0 0 { name=p12 lab=AA[3:0] } C {iopin.sym} 100 -140 0 0 { name=p12 lab=AA[3:0] }
C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[22:1]} C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[22:1]}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"} C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {lab_pin.sym} 1410 -620 0 1 {name=p8 lab=ZZ[9]} C {lab_pin.sym} 1410 -620 0 1 {name=p8 lab=ZZ[9]}
@ -359,3 +365,7 @@ C {doublepin.sym} 2510 -980 0 1 {name=x30
net_name=true} net_name=true}
C {lab_pin.sym} 2330 -930 0 0 {name=p5 lab=ZZ[22]} C {lab_pin.sym} 2330 -930 0 0 {name=p5 lab=ZZ[22]}
C {xcross.sym} 2060 -1410 2 0 {name=x31} C {xcross.sym} 2060 -1410 2 0 {name=x31}
C {use.sym} 1590 -100 0 0 {------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;}

4
xschem_library/examples/xcross.sch
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@ -7,3 +7,7 @@ S {}
E {} E {}
C {iopin.sym} 10 -80 0 0 {name=p1 lab=A} C {iopin.sym} 10 -80 0 0 {name=p1 lab=A}
C {iopin.sym} 10 -20 0 0 {name=p1 lab=B} C {iopin.sym} 10 -20 0 0 {name=p1 lab=B}
C {use.sym} 160 -240 0 0 {------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;}

2
xschem_library/ngspice/inv_ngspice.sym
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@ -3,6 +3,8 @@ v {xschem version=3.1.0 file_version=1.2
G {} G {}
K {type=subcircuit K {type=subcircuit
verilog_primitive=true verilog_primitive=true
vhdl_primitive=true
vhdl_format="@@Y <= @@A after 90 ps;"
verilog_format="assign #90 @@Y = ~@@A ;" verilog_format="assign #90 @@Y = ~@@A ;"
format="@name @pinlist @symname ROUT=@ROUT" format="@name @pinlist @symname ROUT=@ROUT"
template="name=x1 ROUT=1000" template="name=x1 ROUT=1000"