fix typos in html doc

doc/xschem_man/commands.html

@@ -172,7 +172,7 @@ shift+ctrl  'F'         Zoom full selected elements
 shift       'G'         Double snap factor
 -           'g'         Half snap factor
 ctrl        'g'         Set snap factor
-alt         'g'         Hilight selected nets and send to gaw waveform viewer
+alt         'g'         Highlight selected nets and send to gaw waveform viewer
 -           'h'         Constrained horizontal move/copy of objects
 alt         'h'         create symbol pins from schematic pins
 ctrl        'h'         Follow http link or execute command (url, tclcommand properties)
@@ -189,8 +189,8 @@ shift       'J'         create xplot plot file for ngspice in simulation directo
 -           'j'         Print list of highlighted nets/pins
 -           'k'         Hilight selected nets
 ctrl+shift  'K'         highlight net passing through elements with 'propag' property set on pins
-shift       'K'         Unhilight all nets
+shift       'K'         Unhighlight all nets
-ctrl        'k'         Unhilight selected nets
+ctrl        'k'         Unhighlight selected nets
 alt         'k'         Select all nets attached to selected wire / label / pin.
 -           'l'         Start line
 ctrl        'l'         Make schematic view from selected symbol
@@ -301,7 +301,7 @@ set replace_key(w) Shift-W
  </p>
  <img src="commands7.png">
  <p>
-  More objects can be rezized. You can add vertex/endpoints by pressing Ctrl and Shift and dragging the mouse 
+  More objects can be resized. You can add vertex/endpoints by pressing Ctrl and Shift and dragging the mouse 
   to enclose another vertex/endpoint. After selecting all desired elements pressing the <kbd>m</kbd> key
   will resize all objects.
  </p>
@@ -373,7 +373,7 @@ set replace_key(w) Shift-W
  <img src="commands12.png">
  <p> Clicking one control point with the <kbd>Ctrl</kbd> key will delete a point in the polygon shape.</p>
  <p> Adding attribute <kbd>bezier=true</kbd> or  <kbd>bezier=1</kbd> will transform the polygon into a bezier
-  cuve with the polygon points acting as control points.</p>
+  curve with the polygon points acting as control points.</p>
  <img src="commands13.png">
 
 

doc/xschem_man/component_property_syntax.html

@@ -73,7 +73,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
     else, provided the names are different. XSCHEM enforces this, 
     unless <kbd>Options -&gt; allow duplicated instance names</kbd> is set. If a name is given that already
     exist in the current schematic it will be renamed. Normally the template string defines a default
-    name for a given component, and expecially for SPICE compatibility, the first character must NOT 
+    name for a given component, and especially for SPICE compatibility, the first character must NOT 
     be changed. For example, the default name for a MOS transistor is <kbd>m1</kbd>, it can be renamed
     for example to <kbd>mcurr_source</kbd> but not for example to <kbd>dcurr_source</kbd>. XSCHEM 
     does not enforce that the first character is preserved, it's up to the designer to keep it 
@@ -94,7 +94,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
   </p>
   <li><kbd>url</kbd></li>
   <p> This attribute defines a location (web page, file) that can be viewed when hitting the
-    <kbd>&lt;shift&gt;H</kbd> key (or <kbd>&lt;Alt&gt; left mouse buttoni</kbd>) on a selected component. 
+    <kbd>&lt;shift&gt;H</kbd> key (or <kbd>&lt;Alt&gt; left mouse button</kbd>) on a selected component. 
     This is very useful to link a datasheet to a
     component, for example. The default program used to open the url is <kbd>xdg-open</kbd>. 
     this can be changed in the <kbd>~/xschemrc</kbd> configuration file with the <kbd>launcher_default_program</kbd>
@@ -113,9 +113,9 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
   <img src="component_properties3.png">
   <li><kbd>only_toplevel</kbd></li>
   <p>this attribute is valid only on <kbd>netlist_commands</kbd> type symbols and specifies that the 
-    symbol should be netlisted only if it is instantiated in the top-most hierarchy. This is very usefull
+    symbol should be netlisted only if it is instantiated in the top-most hierarchy. This is very useful
     for spice commands. Spice commands are placed in a special <kbd>netlist</kbd> component as we will see
-    and are meaningfull only when simulating the block, but should be skipped if the component
+    and are meaningful only when simulating the block, but should be skipped if the component
     is simulated as part of a bigger system which has its own (at higher hierarchy level)
     <kbd>netlist</kbd>component for Spice commands.</p>
   <img src="component_properties0.png">
@@ -175,7 +175,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
    <kbd>lvs_ignore</kbd> is set to <kbd>1</kbd>. This can be done in the Simulation menu:
    <kbd>Set 'lvs_ignore' variable</kbd>. If this <kbd>lvs_ignore</kbd> is set on the instance
    it will be shorted / ignored or kept as is depending on its <kbd>lvs_ignore</kbd> attribute
-   and will be effective in all netlising formats. This is mostly used to modify the produced netlist
+   and will be effective in all netlisting formats. This is mostly used to modify the produced netlist
    automatically when doing schematic vs layout (LVS) comparison.</p>
 
   <p> By using the <kbd>*_ignore</kbd> attributes you can modify the circuit depending on the value of a tcl variable:</p>
@@ -201,7 +201,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
   <p>
    In this example a <kbd>verilog_include_file.v</kbd> is included using the verilog <kbd>`include</kbd> directive.
    In order to generate a full path for it the <kbd>abs_sym_path</kbd> TCL function is used that searches for this file
-   in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrappend into a tcleval(...),<br>
+   in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrapped into a tcleval(...),<br>
    The following will appear in the generated netlist:
    <pre class="code">
 // expanding   symbol:  verilog_include.sym # of pins=3 

doc/xschem_man/creating_schematic.html

@@ -68,7 +68,7 @@ p{padding: 15px  30px 10px;}
  <p>
   Finally we must connect the input and output port connectors, and to complete the gate schematic
   we decide to use W=8u for the pmos transistors. Select both the pmos devices and press the 
-  edit proprty <kbd>'q'</kbd> key; modify from 5u (default) to 8u.
+  edit property <kbd>'q'</kbd> key; modify from 5u (default) to 8u.
  </p>
  <img src="creating_schematic7.png"> 
  <p>
@@ -101,7 +101,7 @@ p{padding: 15px  30px 10px;}
   and pressing the <kbd>Delete</kbd> key) all the green lines, keep the red pins, the pin labels and the 
   @symname and @name texts, then draw a nand shape like in the following picture. 
   To allow you to draw small 
-  segments you may need to reduce the snap factor (menu <kbd>View-&gt;Half snap thresholf</kbd>)
+  segments you may need to reduce the snap factor (menu <kbd>View-&gt;Half snap threshold</kbd>)
   remember to reset the snap factor to its default setting when done.
  </p>
  <img src="creating_schematic11.png"> 

doc/xschem_man/developer_info.html

@@ -34,7 +34,7 @@ p{padding: 15px  30px 10px;}
  </ol>
  <p>
   These primitive objects can be drawn on any layer. XSCHEM number of layers can be defined at compile
-  time, however there are some predefiend layers (from 0 to 5) that have specific functions:
+  time, however there are some predefined layers (from 0 to 5) that have specific functions:
  </p>
  <ol start="0">
  <li>Background color</li>
@@ -103,7 +103,7 @@ p{padding: 15px  30px 10px;}
  </p>
  <img src="developer_info_02.png">
  <p>
-  When drawing objecs in XSCHEM coordinates are snapped to a multiple of 10.0 coordinate units,
+  When drawing objects in XSCHEM coordinates are snapped to a multiple of 10.0 coordinate units,
   so all drawn objects are easily aligned.
   The snap level can be changed to any value by the user to allow drawing small objects if desired.
   Grid points are shown at multiples of 20.0 coordinate units, by default.

doc/xschem_man/graphs.html

@@ -263,7 +263,7 @@ The following syntax:
   loaded from a common .raw file.
   Image below shows an example: DC, AC, Transient simulation each one done with 3 runs
   varying the Bias current. In addition the <kbd>xschem annotate_op</kbd> is also used to 
-  annotate the operating point into teh schematic.
+  annotate the operating point into the schematic.
   Ctrl-Left-button-clicking the <kbd>Backannotate</kbd> launcher will instantly update
   all graphs with data taken from the updated raw file(s).
   <br>
@@ -276,7 +276,7 @@ The following syntax:
   <kbd>"alias_name; signal_name % dataset# raw_file sim_type</kbd><br>
    where:<br>
    <kbd>dataset#</kbd> is the dataset index to display (only meaningful and needed
-   if multiple datasets are present like in Montecarloo / Mismatch simulations).
+   if multiple datasets are present like in Montecarlo / Mismatch simulations).
    If empty or -1 then show all datasets.<br>
    <kbd>raw_file</kbd> is the location and name of the raw file to load. You can use 
    <kbd>$netlist_dir</kbd> to quickly reference the simulation directory where usually such

doc/xschem_man/net_probes.html

@@ -21,7 +21,7 @@ p{padding: 15px  30px 10px;}
  <!-- slide title -->
  <h1>NET PROBES</h1><br>
  <p>
-  XSCHEM has the ability to hilight a net and propagate the highlight color to all nets or
+  XSCHEM has the ability to highlight a net and propagate the highlight color to all nets or
   instance pins attached to the net. It has the ability to follow this net through the hierarchy. This is very
   useful in large designs as it makes it easy to see where a net is driven and were the net goes (fan-out).
   Highlighting a net is straightforward, click a net and press the <kbd>'k'</kbd> key. If more nets are selected

doc/xschem_man/netlisting.html

@@ -65,7 +65,7 @@ p{padding: 15px  30px 10px;}
  <kbd>subcircuit</kbd> components:
  </p>
  <ul>
- <li><kbd>leaf</kbd>: these componens are 'known' to the simulator, 
+ <li><kbd>leaf</kbd>: these components are 'known' to the simulator, 
   netlist of these blocks is done by specifying a 'format' attribute in the symbol 
   property string. Examples of leaf components in the schematic above are voltage sources,
   resistors, capacitors, dependent sources. The following are examples of leaf component

doc/xschem_man/parameters.html

@@ -64,7 +64,7 @@ p{padding: 15px  30px 10px;}
   Now close the modified symbol saving the changes. Let's test the placement of the 
   new modified symbol. Start a new
   schematic (menu <kbd>File -&gt; New</kbd>) and insert (<kbd>Insert key</kbd>)
-  the NAND2 gate. by pressing <kbd>'q'</kbd> you are now able to speciify different values
+  the NAND2 gate. by pressing <kbd>'q'</kbd> you are now able to specify different values
   for the geometric parameters:
  </p>
  <img src="parameters5.png">

doc/xschem_man/run_xschem.html

@@ -52,7 +52,7 @@ Options:
   -n  --netlist        Do a netlist of the given schematic cell.
   -v  --version        Print version information and exit.
   -V  --vhdl           Set netlist type to VHDL.
-  -S  --simulate       Run a simulation of the current schematc file 
+  -S  --simulate       Run a simulation of the current schematic file 
                        (spice/Verilog/VHDL, depending on the netlist 
                        type chosen).
   -w  --verilog        Set netlist type to Verilog.
@@ -73,7 +73,7 @@ Options:
   -s  --spice          Set netlist type to SPICE.
   -y  --symbol         Set netlist type to SYMBOL (used when drawing symbols)
   -x  --no_x           Don't use X (only command mode).
-  -z  --rainbow        Use a raibow-looking layer color table.
+  -z  --rainbow        Use a rainbow-looking layer color table.
   -W  --waves          Show simulation waveforms.
   -f  --flat_netlist   Set flat netlist (for spice format only).
   -r  --no_readline    Start without the tclreadline package, this is necessary

doc/xschem_man/simulation.html

@@ -68,7 +68,7 @@ xrdb -merge ~/.Xresources
   The text entry on the verilog line is the command to invoke icarus verilog simulation. <kbd>$N</kbd>
   will be expanded to the netlist file (<kbd>$netlist_dir/greycnt.v</kbd>), while <kbd>$n</kbd>
   will be replaced with the circuit name without extension (<kbd>$netlist_dir/greycnt</kbd>).
-  Note also the command to invoke gtkwave on the vcd file generated by theverilog simulation.
+  Note also the command to invoke gtkwave on the vcd file generated by the verilog simulation.
   If <kbd>Save Configuration</kbd> button is pressed the changes are made permanent by saving 
   in a <kbd>~/.xschem/simrc</kbd> file.
  </p>

doc/xschem_man/subckt_with_parameters.html

@@ -25,7 +25,7 @@ p{padding: 15px  30px 10px;}
  </p>
  <ul>
   <li>GAIN: The differential maximum small signal gain of the opamp.</li>
-  <li>AMPLITUDE: The peak to peak swing ot the opamp output.</li>
+  <li>AMPLITUDE: The peak to peak swing of the opamp output.</li>
   <li>OFFSET: the offset of the output when input differential signal is zero.<br>
       For example giving AMPLITUDE=10 and OFFSET=5 will result in an output swing from 0 to +10V.</li>
   <li>ROUT: the output resistance.</li>
@@ -40,7 +40,7 @@ p{padding: 15px  30px 10px;}
  </p>
  <img src="subckt_with_parameters01.png"> 
  <p>
-  after drawig the schematic a symbol is created. The easiest way is to press the 'a' key in the
+  after drawing the schematic a symbol is created. The easiest way is to press the 'a' key in the
   schematic to automatically create the symbol, then descend into the symbol and do some artwork to 
   reshape it to represent an opamp.<br>
   After reshaping the symbol edit its global attributes and add handling of subcircuit parameters 

doc/xschem_man/symbol_property_syntax.html

@@ -45,14 +45,14 @@ p{padding: 15px  30px 10px;}
      file even if it exists. Xschem will not allow to descend into an existing schematic.</li>
     <li><kbd>label</kbd>: the symbol is used to label a net. These type of symbols must have
      one and only one pin, and the template string must define a <kbd>lab</kbd> attribute
-     that is passed at component instantiationi to name the net it is attached to. </li>
+     that is passed at component instantiation to name the net it is attached to. </li>
     <li><kbd>probe</kbd>: this denotes a probe symbol that may be backannotated with a
      backannotation script (example: ngspice_backannotate.tcl).</li>
     <li><kbd>ngprobe</kbd>: This is a probe element that uses a 'pull' method to fetch simulation 
      data and display it in current schematic. The data displayed is thus dynamic, multiple
-     instancs of the same symbol with annotators will display operating point data for that particular
+     instances of the same symbol with annotators will display operating point data for that particular
      instance without the need to update the backannotation as is required for annotators 
-     using the 'push' annotation methid.</li>
+     using the 'push' annotation method.</li>
     <li><kbd>netlist_commands</kbd>: the symbol is used to place SPICE commands into a spice netlist.
      It should also have a <kbd>value</kbd> attribute that may contain arbitrary text that is 
      copied verbatim into the netlist. More on this in the <a href="...">netlist</a> slide.</li>
@@ -174,7 +174,7 @@ type=nmos
    <kbd>lvs_ignore</kbd> is set to <kbd>1</kbd>. This can be done in the Simulation menu:
    <kbd>Set 'lvs_ignore' variable</kbd>. If this <kbd>lvs_ignore</kbd> is set on the symbol
    it will be shorted / ignored or kept as is depending on its <kbd>lvs_ignore</kbd> attribute
-   and will be effective in all netlising formats. This is mostly used to modify the produced netlist
+   and will be effective in all netlisting formats. This is mostly used to modify the produced netlist
    automatically when doing schematic vs layout (LVS) comparison.</p>
 
 
@@ -199,7 +199,7 @@ type=nmos
   <li><kbd>default_schematic</kbd></li>
   <p> If set to <kbd>ignore</kbd> xschem will not descend into the symbol associated schematic and will
    not complain if this schematic does not exists. To descend into a schematic instances must specify a 
-   <kbd>schematic</kbd> attribute, otherwise no descendng and expansion occurs.</p>
+   <kbd>schematic</kbd> attribute, otherwise no descending and expansion occurs.</p>
 
   <li><kbd>spice_sym_def</kbd></li>
   <li><kbd>verilog_sym_def</kbd></li>
@@ -219,7 +219,7 @@ type=nmos
   <p>
    In this example a <kbd>verilog_include_file.v</kbd> is included using the verilog <kbd>`include</kbd> directive.
    In order to generate a full path for it the <kbd>abs_sym_path</kbd> TCL function is used that searches for this file
-   in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrappend into a tcleval(...),<br>
+   in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrapped into a tcleval(...),<br>
    The following will appear in the generated netlist:
    <pre class="code">
 // expanding   symbol:  verilog_include.sym # of pins=3
@@ -236,7 +236,7 @@ type=nmos
   <p> This attribute is only useable in <kbd>netlist_commands</kbd> type symbols (<kbd>netlist.sym, code.sym,...</kbd>) 
     if set to <kbd>end</kbd> it tells XSCHEM that 
     the component instance of that symbol must be netlisted at the end, after all the other elements.
-    This is sometimes needed for SPICE commands that must ge given at the end of the netlist.
+    This is sometimes needed for SPICE commands that must given at the end of the netlist.
     This will be explained more in detail in the <a href="...">netlisting</a> slide.
     <br>
     The <kbd>place=header</kbd> attribute is only valid only for netlist_commands
@@ -359,7 +359,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
   <li><kbd>verilog_extra</kbd></li>
   <p> 
   This attribute is similar to the <kbd>extra</kbd> attribute and is used for verilog netlist. Nodes
-  listed in this atrribute value will be used as additional pin connections.
+  listed in this attribute value will be used as additional pin connections.
   </p>
   <p class="important">
   the <kbd>extra</kbd> attribute is still used in verilog netlist as a list of attributes NOT to pass as
@@ -438,7 +438,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
   <p>
   This attribute is used in the xschem embedded digital simulation engine: propagate logic simulation
   to the output pins <kbd>n,[m,...]</kbd>. The logic function is defined via the 'function<kbd>n</kbd>'
-  global attribute. There is one 'funtion<kbd>n</kbd>' for each <kbd>n</kbd> output pin.
+  global attribute. There is one 'function<kbd>n</kbd>' for each <kbd>n</kbd> output pin.
   see 'function<kbd>n</kbd>' attribute for more info.
   </p>
    <img src="symbol_property_syntax4.png">
@@ -476,7 +476,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
      <li> <kbd>m</kbd>: same as above, but don't update if 'm' not 1 or 0. Used to avoid deadlocks.</li>
      <li> <kbd>z</kbd>: preceeded by 2 elements, 'a', 'e', return 'a' if 'e' == 1 else Z (hi-Z)</li>
      <li> <kbd>d</kbd>: Duplicates top element on the stack</li>
-     <li> <kbd>x</kbd>: Exhanges the 2 top elements on the stack</li>
+     <li> <kbd>x</kbd>: Exchanges the 2 top elements on the stack</li>
      <li> <kbd>r</kbd>: Rotate down: bottom element of stack goes to top</li>
      <li> <kbd>H</kbd>: Puts a Logic '1' on the stack</li>
      <li> <kbd>L</kbd>: Puts a Logic '0' on the stack</li>
@@ -642,19 +642,19 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
   </p>
   <li><kbd>@prop_ptr</kbd></li>
   <p>
-   this expandes to the <b>entire</b> property string passed to the component.
+   this expands to the <b>entire</b> property string passed to the component.
   </p>
   <li><kbd>@schprop</kbd></li>
   <p>
-   this expandes to the <b>spice</b> global property string of the schematic containing the symbol
+   this expands to the <b>spice</b> global property string of the schematic containing the symbol
   </p>
   <li><kbd>@schvhdlprop</kbd></li>
   <p>
-   this expandes to the <b>VHDL</b> global property string of the schematic containing the symbol
+   this expands to the <b>VHDL</b> global property string of the schematic containing the symbol
   </p>
   <li><kbd>@schverilogprop</kbd></li>
   <p>
-   this expandes to the <b>Verilog</b> global property string of the schematic containing the symbol
+   this expands to the <b>Verilog</b> global property string of the schematic containing the symbol
   </p>
  </ul><br>
  <h3>TCL ATTRIBUTE SUBSTITUTION</h3>

doc/xschem_man/tutorial_instance_based_implementation.html

@@ -57,7 +57,7 @@ p{padding: 15px  30px 10px;}
  <h3> spice_sym_def attribute on instance </h3>
  <p>
   A <kbd>spice_sym_def=&lt;...text...&gt;</kbd> attribute attached to an instance will specify some text that describes 
-  the subcircuit (it can be a simplified spice subcircuit netlist or a spice .include line that gets the  subcircuit from
+  the subcircuit (it can be a simplified spice subcircuit netlist or a spice .include line that gets the subcircuit from
   an external file). This attribute on an instance must always be paired with a matching <kbd>schematic</kbd> attribute
   that specifies the subcircuit name the instance is linked to. 
  </p>
@@ -100,10 +100,10 @@ spice_sym_def="
  <pre class="code">
 spice_sym_def=".include /path/to/subckt_file" </pre>
  <p>
- Xchem will use the port order provided in the subckt line, either by looking directly into the attribute value
+ Xschem will use the port order provided in the subckt line, either by looking directly into the attribute value
  or by loading the file specified by the .include line. This way there will not be inconsistencies
  between instance line and subckt definition in the circuit netlist. If for some reason the port list can not be read or
- pin names do not match xchem will use the port order drom the <kbd>.sym</kbd> file.
+ pin names do not match xschem will use the port order drom the <kbd>.sym</kbd> file.
  </p><br><br>
 
  <p class="important">

doc/xschem_man/tutorial_run_simulation.html

@@ -72,7 +72,7 @@ p{padding: 15px  30px 10px;}
  <img src="tutorial_run_simulation_08.png"> 
  
  
- <li>Cosmetics: add 'title.sym' move the circuit (by selecting it dragging the mouse and pressing 'm', if needed).  Note that you can do a 'stretch move'operation if you need move components keeping the wires attached; refer to the xschem manual <a href="http://repo.hu/projects/xschem/xschem_man/commands.html">here</a></li>
+ <li>Cosmetics: add 'title.sym' move the circuit (by selecting it dragging the mouse and pressing 'm', if needed).  Note that you can do a 'stretch move' operation if you need move components keeping the wires attached; refer to the xschem manual <a href="http://repo.hu/projects/xschem/xschem_man/commands.html">here</a></li>
  
  <img src="tutorial_run_simulation_09.png"> 
  

doc/xschem_man/tutorial_use_existing_subckt.html

@@ -63,13 +63,13 @@ template="name=x1"
  <img src="tutorial_use_existing_subckt03.png"> 
  <p>
   This will put the selected pin in first position. 
-  Then move to the pin you want in second position, repeat above steps and assing to it index number 1,
+  Then move to the pin you want in second position, repeat above steps and assign to it index number 1,
   and so on for all the symbol pins. At the end save your symbol and this will be the pin
   ordering in netlists.
   When netlist is produced this order will be used.
   If left pins in above example have sequence numbers of (starting from the top) 0, 1, 2, 3 and
   right pins have sequence numbers (starting from the bottom) 4, 5, 6, 7 the instance line in 
-  the netlist will be (check the net names with the schematc in the first image above):
+  the netlist will be (check the net names with the schematic in the first image above):
  </p>
  <pre class="code"> 
 x1 VSS TRIG OUT VSUPPLY CTRL TRIG DIS VSUPPLY ne555

doc/xschem_man/xschem_elements.html

@@ -105,7 +105,7 @@ p{padding: 15px  30px 10px;}
   </p>  
   <img src="xschem_elements_02.png">
   <p>
-   You wil learn in the <a href="xschem_properties.html">xschem properties chapter</a>
+   You will learn in the <a href="xschem_properties.html">xschem properties chapter</a>
    how to set, edit and change object properties.
   </p>
   <img src="xschem_texts1.png">

doc/xschem_man/xschem_properties.html

@@ -49,7 +49,7 @@ p{padding: 15px  30px 10px;}
   The property string also defines a <kbd>dir</kbd> attribute with value
   <kbd>inout</kbd>. This tells XSCHEM that electrically this is an input/output pin.
   This is important when producing VHDL/verilog netlists.
-  The <kbd>propag=1</kbd> tells XSCHEM that when we select a wire attaced to this pin
+  The <kbd>propag=1</kbd> tells XSCHEM that when we select a wire attached to this pin
   (which is located at index 0 in xschem) the highlight will propagate to the other pin (with index 1).
   To view the xschem index of a pin click and hold the mouse on it, the index will be shown as 
   <kbd>n= &lt;number&gt; </kbd> in the bottom status line:

doc/xschem_man/xschem_remote.html

@@ -60,7 +60,7 @@ p{padding: 15px  30px 10px;}
   The following shell script fragment shows the commands to be used to negotiate with xschem another tcp port.<br>
   The <kbd>nc</kbd> (netcat) utility is used to pipe the commands to the tcp socket.<br>
   When starting xschem a fixed initial port number is always used (2021 by default), so it is always possible to
-  remotely communicate with xschem using this TCP port. Then the following comands can be sent to setup a new port number
+  remotely communicate with xschem using this TCP port. Then the following commands can be sent to setup a new port number
   for further communications, freeing the initial (2021) port number. If another xschem process is started it will 
   again use the initial port number, so no port number collisions occur.
  </p>
@@ -77,7 +77,7 @@ schippes@asus:~$ b=$(echo 'xschem get current_name' |nc localhost "$a")
 schippes@asus:~$ echo "$b"
 untitled.sch
 
-## repeat above steps if you want additional xschem instances each listenng to a different free tcp port.
+## repeat above steps if you want additional xschem instances each listening to a different free tcp port.
 
  </pre>