fix typos in html doc
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@ -172,7 +172,7 @@ shift+ctrl 'F' Zoom full selected elements
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shift 'G' Double snap factor
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- 'g' Half snap factor
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ctrl 'g' Set snap factor
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alt 'g' Hilight selected nets and send to gaw waveform viewer
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alt 'g' Highlight selected nets and send to gaw waveform viewer
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- 'h' Constrained horizontal move/copy of objects
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alt 'h' create symbol pins from schematic pins
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ctrl 'h' Follow http link or execute command (url, tclcommand properties)
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@ -189,8 +189,8 @@ shift 'J' create xplot plot file for ngspice in simulation directo
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- 'j' Print list of highlighted nets/pins
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- 'k' Hilight selected nets
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ctrl+shift 'K' highlight net passing through elements with 'propag' property set on pins
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shift 'K' Unhilight all nets
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ctrl 'k' Unhilight selected nets
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shift 'K' Unhighlight all nets
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ctrl 'k' Unhighlight selected nets
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alt 'k' Select all nets attached to selected wire / label / pin.
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- 'l' Start line
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ctrl 'l' Make schematic view from selected symbol
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@ -301,7 +301,7 @@ set replace_key(w) Shift-W
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</p>
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<img src="commands7.png">
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<p>
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More objects can be rezized. You can add vertex/endpoints by pressing Ctrl and Shift and dragging the mouse
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More objects can be resized. You can add vertex/endpoints by pressing Ctrl and Shift and dragging the mouse
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to enclose another vertex/endpoint. After selecting all desired elements pressing the <kbd>m</kbd> key
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will resize all objects.
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</p>
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@ -373,7 +373,7 @@ set replace_key(w) Shift-W
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<img src="commands12.png">
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<p> Clicking one control point with the <kbd>Ctrl</kbd> key will delete a point in the polygon shape.</p>
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<p> Adding attribute <kbd>bezier=true</kbd> or <kbd>bezier=1</kbd> will transform the polygon into a bezier
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cuve with the polygon points acting as control points.</p>
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curve with the polygon points acting as control points.</p>
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<img src="commands13.png">
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@ -73,7 +73,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
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else, provided the names are different. XSCHEM enforces this,
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unless <kbd>Options -> allow duplicated instance names</kbd> is set. If a name is given that already
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exist in the current schematic it will be renamed. Normally the template string defines a default
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name for a given component, and expecially for SPICE compatibility, the first character must NOT
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name for a given component, and especially for SPICE compatibility, the first character must NOT
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be changed. For example, the default name for a MOS transistor is <kbd>m1</kbd>, it can be renamed
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for example to <kbd>mcurr_source</kbd> but not for example to <kbd>dcurr_source</kbd>. XSCHEM
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does not enforce that the first character is preserved, it's up to the designer to keep it
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@ -94,7 +94,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
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</p>
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<li><kbd>url</kbd></li>
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<p> This attribute defines a location (web page, file) that can be viewed when hitting the
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<kbd><shift>H</kbd> key (or <kbd><Alt> left mouse buttoni</kbd>) on a selected component.
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<kbd><shift>H</kbd> key (or <kbd><Alt> left mouse button</kbd>) on a selected component.
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This is very useful to link a datasheet to a
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component, for example. The default program used to open the url is <kbd>xdg-open</kbd>.
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this can be changed in the <kbd>~/xschemrc</kbd> configuration file with the <kbd>launcher_default_program</kbd>
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@ -113,9 +113,9 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
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<img src="component_properties3.png">
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<li><kbd>only_toplevel</kbd></li>
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<p>this attribute is valid only on <kbd>netlist_commands</kbd> type symbols and specifies that the
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symbol should be netlisted only if it is instantiated in the top-most hierarchy. This is very usefull
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symbol should be netlisted only if it is instantiated in the top-most hierarchy. This is very useful
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for spice commands. Spice commands are placed in a special <kbd>netlist</kbd> component as we will see
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and are meaningfull only when simulating the block, but should be skipped if the component
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and are meaningful only when simulating the block, but should be skipped if the component
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is simulated as part of a bigger system which has its own (at higher hierarchy level)
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<kbd>netlist</kbd>component for Spice commands.</p>
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<img src="component_properties0.png">
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@ -175,7 +175,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
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<kbd>lvs_ignore</kbd> is set to <kbd>1</kbd>. This can be done in the Simulation menu:
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<kbd>Set 'lvs_ignore' variable</kbd>. If this <kbd>lvs_ignore</kbd> is set on the instance
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it will be shorted / ignored or kept as is depending on its <kbd>lvs_ignore</kbd> attribute
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and will be effective in all netlising formats. This is mostly used to modify the produced netlist
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and will be effective in all netlisting formats. This is mostly used to modify the produced netlist
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automatically when doing schematic vs layout (LVS) comparison.</p>
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<p> By using the <kbd>*_ignore</kbd> attributes you can modify the circuit depending on the value of a tcl variable:</p>
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@ -201,7 +201,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
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<p>
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In this example a <kbd>verilog_include_file.v</kbd> is included using the verilog <kbd>`include</kbd> directive.
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In order to generate a full path for it the <kbd>abs_sym_path</kbd> TCL function is used that searches for this file
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in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrappend into a tcleval(...),<br>
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in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrapped into a tcleval(...),<br>
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The following will appear in the generated netlist:
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<pre class="code">
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// expanding symbol: verilog_include.sym # of pins=3
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@ -68,7 +68,7 @@ p{padding: 15px 30px 10px;}
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<p>
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Finally we must connect the input and output port connectors, and to complete the gate schematic
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we decide to use W=8u for the pmos transistors. Select both the pmos devices and press the
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edit proprty <kbd>'q'</kbd> key; modify from 5u (default) to 8u.
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edit property <kbd>'q'</kbd> key; modify from 5u (default) to 8u.
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</p>
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<img src="creating_schematic7.png">
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<p>
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@ -101,7 +101,7 @@ p{padding: 15px 30px 10px;}
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and pressing the <kbd>Delete</kbd> key) all the green lines, keep the red pins, the pin labels and the
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@symname and @name texts, then draw a nand shape like in the following picture.
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To allow you to draw small
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segments you may need to reduce the snap factor (menu <kbd>View->Half snap thresholf</kbd>)
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segments you may need to reduce the snap factor (menu <kbd>View->Half snap threshold</kbd>)
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remember to reset the snap factor to its default setting when done.
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</p>
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<img src="creating_schematic11.png">
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@ -34,7 +34,7 @@ p{padding: 15px 30px 10px;}
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</ol>
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<p>
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These primitive objects can be drawn on any layer. XSCHEM number of layers can be defined at compile
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time, however there are some predefiend layers (from 0 to 5) that have specific functions:
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time, however there are some predefined layers (from 0 to 5) that have specific functions:
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</p>
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<ol start="0">
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<li>Background color</li>
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@ -103,7 +103,7 @@ p{padding: 15px 30px 10px;}
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</p>
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<img src="developer_info_02.png">
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<p>
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When drawing objecs in XSCHEM coordinates are snapped to a multiple of 10.0 coordinate units,
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When drawing objects in XSCHEM coordinates are snapped to a multiple of 10.0 coordinate units,
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so all drawn objects are easily aligned.
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The snap level can be changed to any value by the user to allow drawing small objects if desired.
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Grid points are shown at multiples of 20.0 coordinate units, by default.
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@ -263,7 +263,7 @@ The following syntax:
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loaded from a common .raw file.
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Image below shows an example: DC, AC, Transient simulation each one done with 3 runs
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varying the Bias current. In addition the <kbd>xschem annotate_op</kbd> is also used to
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annotate the operating point into teh schematic.
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annotate the operating point into the schematic.
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Ctrl-Left-button-clicking the <kbd>Backannotate</kbd> launcher will instantly update
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all graphs with data taken from the updated raw file(s).
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<br>
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@ -276,7 +276,7 @@ The following syntax:
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<kbd>"alias_name; signal_name % dataset# raw_file sim_type</kbd><br>
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where:<br>
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<kbd>dataset#</kbd> is the dataset index to display (only meaningful and needed
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if multiple datasets are present like in Montecarloo / Mismatch simulations).
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if multiple datasets are present like in Montecarlo / Mismatch simulations).
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If empty or -1 then show all datasets.<br>
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<kbd>raw_file</kbd> is the location and name of the raw file to load. You can use
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<kbd>$netlist_dir</kbd> to quickly reference the simulation directory where usually such
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@ -21,7 +21,7 @@ p{padding: 15px 30px 10px;}
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<!-- slide title -->
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<h1>NET PROBES</h1><br>
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<p>
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XSCHEM has the ability to hilight a net and propagate the highlight color to all nets or
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XSCHEM has the ability to highlight a net and propagate the highlight color to all nets or
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instance pins attached to the net. It has the ability to follow this net through the hierarchy. This is very
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useful in large designs as it makes it easy to see where a net is driven and were the net goes (fan-out).
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Highlighting a net is straightforward, click a net and press the <kbd>'k'</kbd> key. If more nets are selected
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@ -65,7 +65,7 @@ p{padding: 15px 30px 10px;}
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<kbd>subcircuit</kbd> components:
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</p>
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<ul>
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<li><kbd>leaf</kbd>: these componens are 'known' to the simulator,
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<li><kbd>leaf</kbd>: these components are 'known' to the simulator,
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netlist of these blocks is done by specifying a 'format' attribute in the symbol
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property string. Examples of leaf components in the schematic above are voltage sources,
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resistors, capacitors, dependent sources. The following are examples of leaf component
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@ -64,7 +64,7 @@ p{padding: 15px 30px 10px;}
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Now close the modified symbol saving the changes. Let's test the placement of the
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new modified symbol. Start a new
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schematic (menu <kbd>File -> New</kbd>) and insert (<kbd>Insert key</kbd>)
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the NAND2 gate. by pressing <kbd>'q'</kbd> you are now able to speciify different values
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the NAND2 gate. by pressing <kbd>'q'</kbd> you are now able to specify different values
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for the geometric parameters:
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</p>
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<img src="parameters5.png">
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@ -52,7 +52,7 @@ Options:
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-n --netlist Do a netlist of the given schematic cell.
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-v --version Print version information and exit.
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-V --vhdl Set netlist type to VHDL.
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-S --simulate Run a simulation of the current schematc file
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-S --simulate Run a simulation of the current schematic file
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(spice/Verilog/VHDL, depending on the netlist
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type chosen).
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-w --verilog Set netlist type to Verilog.
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@ -73,7 +73,7 @@ Options:
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-s --spice Set netlist type to SPICE.
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-y --symbol Set netlist type to SYMBOL (used when drawing symbols)
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-x --no_x Don't use X (only command mode).
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-z --rainbow Use a raibow-looking layer color table.
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-z --rainbow Use a rainbow-looking layer color table.
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-W --waves Show simulation waveforms.
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-f --flat_netlist Set flat netlist (for spice format only).
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-r --no_readline Start without the tclreadline package, this is necessary
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@ -68,7 +68,7 @@ xrdb -merge ~/.Xresources
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The text entry on the verilog line is the command to invoke icarus verilog simulation. <kbd>$N</kbd>
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will be expanded to the netlist file (<kbd>$netlist_dir/greycnt.v</kbd>), while <kbd>$n</kbd>
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will be replaced with the circuit name without extension (<kbd>$netlist_dir/greycnt</kbd>).
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Note also the command to invoke gtkwave on the vcd file generated by theverilog simulation.
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Note also the command to invoke gtkwave on the vcd file generated by the verilog simulation.
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If <kbd>Save Configuration</kbd> button is pressed the changes are made permanent by saving
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in a <kbd>~/.xschem/simrc</kbd> file.
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</p>
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@ -25,7 +25,7 @@ p{padding: 15px 30px 10px;}
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</p>
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<ul>
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<li>GAIN: The differential maximum small signal gain of the opamp.</li>
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<li>AMPLITUDE: The peak to peak swing ot the opamp output.</li>
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<li>AMPLITUDE: The peak to peak swing of the opamp output.</li>
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<li>OFFSET: the offset of the output when input differential signal is zero.<br>
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For example giving AMPLITUDE=10 and OFFSET=5 will result in an output swing from 0 to +10V.</li>
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<li>ROUT: the output resistance.</li>
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@ -40,7 +40,7 @@ p{padding: 15px 30px 10px;}
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</p>
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<img src="subckt_with_parameters01.png">
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<p>
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after drawig the schematic a symbol is created. The easiest way is to press the 'a' key in the
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after drawing the schematic a symbol is created. The easiest way is to press the 'a' key in the
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schematic to automatically create the symbol, then descend into the symbol and do some artwork to
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reshape it to represent an opamp.<br>
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After reshaping the symbol edit its global attributes and add handling of subcircuit parameters
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@ -45,14 +45,14 @@ p{padding: 15px 30px 10px;}
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file even if it exists. Xschem will not allow to descend into an existing schematic.</li>
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<li><kbd>label</kbd>: the symbol is used to label a net. These type of symbols must have
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one and only one pin, and the template string must define a <kbd>lab</kbd> attribute
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that is passed at component instantiationi to name the net it is attached to. </li>
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that is passed at component instantiation to name the net it is attached to. </li>
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<li><kbd>probe</kbd>: this denotes a probe symbol that may be backannotated with a
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backannotation script (example: ngspice_backannotate.tcl).</li>
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<li><kbd>ngprobe</kbd>: This is a probe element that uses a 'pull' method to fetch simulation
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data and display it in current schematic. The data displayed is thus dynamic, multiple
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instancs of the same symbol with annotators will display operating point data for that particular
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instances of the same symbol with annotators will display operating point data for that particular
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instance without the need to update the backannotation as is required for annotators
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using the 'push' annotation methid.</li>
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using the 'push' annotation method.</li>
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<li><kbd>netlist_commands</kbd>: the symbol is used to place SPICE commands into a spice netlist.
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It should also have a <kbd>value</kbd> attribute that may contain arbitrary text that is
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copied verbatim into the netlist. More on this in the <a href="...">netlist</a> slide.</li>
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@ -174,7 +174,7 @@ type=nmos
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<kbd>lvs_ignore</kbd> is set to <kbd>1</kbd>. This can be done in the Simulation menu:
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<kbd>Set 'lvs_ignore' variable</kbd>. If this <kbd>lvs_ignore</kbd> is set on the symbol
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it will be shorted / ignored or kept as is depending on its <kbd>lvs_ignore</kbd> attribute
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and will be effective in all netlising formats. This is mostly used to modify the produced netlist
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and will be effective in all netlisting formats. This is mostly used to modify the produced netlist
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automatically when doing schematic vs layout (LVS) comparison.</p>
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<li><kbd>default_schematic</kbd></li>
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<p> If set to <kbd>ignore</kbd> xschem will not descend into the symbol associated schematic and will
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not complain if this schematic does not exists. To descend into a schematic instances must specify a
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<kbd>schematic</kbd> attribute, otherwise no descendng and expansion occurs.</p>
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<kbd>schematic</kbd> attribute, otherwise no descending and expansion occurs.</p>
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<li><kbd>spice_sym_def</kbd></li>
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<li><kbd>verilog_sym_def</kbd></li>
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@ -219,7 +219,7 @@ type=nmos
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<p>
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In this example a <kbd>verilog_include_file.v</kbd> is included using the verilog <kbd>`include</kbd> directive.
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In order to generate a full path for it the <kbd>abs_sym_path</kbd> TCL function is used that searches for this file
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in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrappend into a tcleval(...),<br>
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in any of the <kbd>XCHEM_LIBRARY_PATH</kbd> directories. Since TCL is used the attribute is wrapped into a tcleval(...),<br>
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The following will appear in the generated netlist:
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<pre class="code">
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// expanding symbol: verilog_include.sym # of pins=3
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<p> This attribute is only useable in <kbd>netlist_commands</kbd> type symbols (<kbd>netlist.sym, code.sym,...</kbd>)
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if set to <kbd>end</kbd> it tells XSCHEM that
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the component instance of that symbol must be netlisted at the end, after all the other elements.
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This is sometimes needed for SPICE commands that must ge given at the end of the netlist.
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This is sometimes needed for SPICE commands that must given at the end of the netlist.
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This will be explained more in detail in the <a href="...">netlisting</a> slide.
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<br>
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The <kbd>place=header</kbd> attribute is only valid only for netlist_commands
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@ -359,7 +359,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
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<li><kbd>verilog_extra</kbd></li>
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<p>
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This attribute is similar to the <kbd>extra</kbd> attribute and is used for verilog netlist. Nodes
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listed in this atrribute value will be used as additional pin connections.
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listed in this attribute value will be used as additional pin connections.
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</p>
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<p class="important">
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the <kbd>extra</kbd> attribute is still used in verilog netlist as a list of attributes NOT to pass as
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@ -438,7 +438,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
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<p>
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This attribute is used in the xschem embedded digital simulation engine: propagate logic simulation
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to the output pins <kbd>n,[m,...]</kbd>. The logic function is defined via the 'function<kbd>n</kbd>'
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global attribute. There is one 'funtion<kbd>n</kbd>' for each <kbd>n</kbd> output pin.
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global attribute. There is one 'function<kbd>n</kbd>' for each <kbd>n</kbd> output pin.
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see 'function<kbd>n</kbd>' attribute for more info.
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</p>
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<img src="symbol_property_syntax4.png">
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@ -476,7 +476,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
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<li> <kbd>m</kbd>: same as above, but don't update if 'm' not 1 or 0. Used to avoid deadlocks.</li>
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<li> <kbd>z</kbd>: preceeded by 2 elements, 'a', 'e', return 'a' if 'e' == 1 else Z (hi-Z)</li>
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<li> <kbd>d</kbd>: Duplicates top element on the stack</li>
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<li> <kbd>x</kbd>: Exhanges the 2 top elements on the stack</li>
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<li> <kbd>x</kbd>: Exchanges the 2 top elements on the stack</li>
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<li> <kbd>r</kbd>: Rotate down: bottom element of stack goes to top</li>
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<li> <kbd>H</kbd>: Puts a Logic '1' on the stack</li>
|
||||
<li> <kbd>L</kbd>: Puts a Logic '0' on the stack</li>
|
||||
|
|
@ -642,19 +642,19 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
|
|||
</p>
|
||||
<li><kbd>@prop_ptr</kbd></li>
|
||||
<p>
|
||||
this expandes to the <b>entire</b> property string passed to the component.
|
||||
this expands to the <b>entire</b> property string passed to the component.
|
||||
</p>
|
||||
<li><kbd>@schprop</kbd></li>
|
||||
<p>
|
||||
this expandes to the <b>spice</b> global property string of the schematic containing the symbol
|
||||
this expands to the <b>spice</b> global property string of the schematic containing the symbol
|
||||
</p>
|
||||
<li><kbd>@schvhdlprop</kbd></li>
|
||||
<p>
|
||||
this expandes to the <b>VHDL</b> global property string of the schematic containing the symbol
|
||||
this expands to the <b>VHDL</b> global property string of the schematic containing the symbol
|
||||
</p>
|
||||
<li><kbd>@schverilogprop</kbd></li>
|
||||
<p>
|
||||
this expandes to the <b>Verilog</b> global property string of the schematic containing the symbol
|
||||
this expands to the <b>Verilog</b> global property string of the schematic containing the symbol
|
||||
</p>
|
||||
</ul><br>
|
||||
<h3>TCL ATTRIBUTE SUBSTITUTION</h3>
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ p{padding: 15px 30px 10px;}
|
|||
<h3> spice_sym_def attribute on instance </h3>
|
||||
<p>
|
||||
A <kbd>spice_sym_def=<...text...></kbd> attribute attached to an instance will specify some text that describes
|
||||
the subcircuit (it can be a simplified spice subcircuit netlist or a spice .include line that gets the subcircuit from
|
||||
the subcircuit (it can be a simplified spice subcircuit netlist or a spice .include line that gets the subcircuit from
|
||||
an external file). This attribute on an instance must always be paired with a matching <kbd>schematic</kbd> attribute
|
||||
that specifies the subcircuit name the instance is linked to.
|
||||
</p>
|
||||
|
|
@ -100,10 +100,10 @@ spice_sym_def="
|
|||
<pre class="code">
|
||||
spice_sym_def=".include /path/to/subckt_file" </pre>
|
||||
<p>
|
||||
Xchem will use the port order provided in the subckt line, either by looking directly into the attribute value
|
||||
Xschem will use the port order provided in the subckt line, either by looking directly into the attribute value
|
||||
or by loading the file specified by the .include line. This way there will not be inconsistencies
|
||||
between instance line and subckt definition in the circuit netlist. If for some reason the port list can not be read or
|
||||
pin names do not match xchem will use the port order drom the <kbd>.sym</kbd> file.
|
||||
pin names do not match xschem will use the port order drom the <kbd>.sym</kbd> file.
|
||||
</p><br><br>
|
||||
|
||||
<p class="important">
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ p{padding: 15px 30px 10px;}
|
|||
<img src="tutorial_run_simulation_08.png">
|
||||
|
||||
|
||||
<li>Cosmetics: add 'title.sym' move the circuit (by selecting it dragging the mouse and pressing 'm', if needed). Note that you can do a 'stretch move'operation if you need move components keeping the wires attached; refer to the xschem manual <a href="http://repo.hu/projects/xschem/xschem_man/commands.html">here</a></li>
|
||||
<li>Cosmetics: add 'title.sym' move the circuit (by selecting it dragging the mouse and pressing 'm', if needed). Note that you can do a 'stretch move' operation if you need move components keeping the wires attached; refer to the xschem manual <a href="http://repo.hu/projects/xschem/xschem_man/commands.html">here</a></li>
|
||||
|
||||
<img src="tutorial_run_simulation_09.png">
|
||||
|
||||
|
|
|
|||
|
|
@ -63,13 +63,13 @@ template="name=x1"
|
|||
<img src="tutorial_use_existing_subckt03.png">
|
||||
<p>
|
||||
This will put the selected pin in first position.
|
||||
Then move to the pin you want in second position, repeat above steps and assing to it index number 1,
|
||||
Then move to the pin you want in second position, repeat above steps and assign to it index number 1,
|
||||
and so on for all the symbol pins. At the end save your symbol and this will be the pin
|
||||
ordering in netlists.
|
||||
When netlist is produced this order will be used.
|
||||
If left pins in above example have sequence numbers of (starting from the top) 0, 1, 2, 3 and
|
||||
right pins have sequence numbers (starting from the bottom) 4, 5, 6, 7 the instance line in
|
||||
the netlist will be (check the net names with the schematc in the first image above):
|
||||
the netlist will be (check the net names with the schematic in the first image above):
|
||||
</p>
|
||||
<pre class="code">
|
||||
x1 VSS TRIG OUT VSUPPLY CTRL TRIG DIS VSUPPLY ne555
|
||||
|
|
|
|||
|
|
@ -105,7 +105,7 @@ p{padding: 15px 30px 10px;}
|
|||
</p>
|
||||
<img src="xschem_elements_02.png">
|
||||
<p>
|
||||
You wil learn in the <a href="xschem_properties.html">xschem properties chapter</a>
|
||||
You will learn in the <a href="xschem_properties.html">xschem properties chapter</a>
|
||||
how to set, edit and change object properties.
|
||||
</p>
|
||||
<img src="xschem_texts1.png">
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ p{padding: 15px 30px 10px;}
|
|||
The property string also defines a <kbd>dir</kbd> attribute with value
|
||||
<kbd>inout</kbd>. This tells XSCHEM that electrically this is an input/output pin.
|
||||
This is important when producing VHDL/verilog netlists.
|
||||
The <kbd>propag=1</kbd> tells XSCHEM that when we select a wire attaced to this pin
|
||||
The <kbd>propag=1</kbd> tells XSCHEM that when we select a wire attached to this pin
|
||||
(which is located at index 0 in xschem) the highlight will propagate to the other pin (with index 1).
|
||||
To view the xschem index of a pin click and hold the mouse on it, the index will be shown as
|
||||
<kbd>n= <number> </kbd> in the bottom status line:
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ p{padding: 15px 30px 10px;}
|
|||
The following shell script fragment shows the commands to be used to negotiate with xschem another tcp port.<br>
|
||||
The <kbd>nc</kbd> (netcat) utility is used to pipe the commands to the tcp socket.<br>
|
||||
When starting xschem a fixed initial port number is always used (2021 by default), so it is always possible to
|
||||
remotely communicate with xschem using this TCP port. Then the following comands can be sent to setup a new port number
|
||||
remotely communicate with xschem using this TCP port. Then the following commands can be sent to setup a new port number
|
||||
for further communications, freeing the initial (2021) port number. If another xschem process is started it will
|
||||
again use the initial port number, so no port number collisions occur.
|
||||
</p>
|
||||
|
|
@ -77,7 +77,7 @@ schippes@asus:~$ b=$(echo 'xschem get current_name' |nc localhost "$a")
|
|||
schippes@asus:~$ echo "$b"
|
||||
untitled.sch
|
||||
|
||||
## repeat above steps if you want additional xschem instances each listenng to a different free tcp port.
|
||||
## repeat above steps if you want additional xschem instances each listening to a different free tcp port.
|
||||
|
||||
</pre>
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue