Make @spice_get_current report Id (drain current) for mos devices (defined as plain mosfets in model (ngspice syntax), may be to extend for Xyce)
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931b348c1a
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b892ad8ac7
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@ -4001,7 +4001,7 @@ const char *translate(int inst, const char* s)
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dbg(1, "prefix=%c, path=%s\n", prefix, path);
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vsource = (prefix == 'v') || (prefix == 'e');
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s.%s)", prefix, path, instname, dev);
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else if(prefix == 'd')
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else if(prefix == 'd' || prefix == 'm')
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my_snprintf(fqdev, len, "i(@%c.%s%s.%s[id])", prefix, path, instname, dev);
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else if(prefix == 'i')
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my_snprintf(fqdev, len, "i(@%c.%s%s.%s[current])", prefix, path, instname, dev);
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@ -4132,12 +4132,12 @@ const char *translate(int inst, const char* s)
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int vsource = (prefix == 'v') || (prefix == 'e');
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if(path[0]) {
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s)", prefix, path, dev);
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else if(prefix=='d') my_snprintf(fqdev, len, "i(@%c.%s%s[id])", prefix, path, dev);
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else if(prefix=='d' || prefix == 'm') my_snprintf(fqdev, len, "i(@%c.%s%s[id])", prefix, path, dev);
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else if(prefix=='i') my_snprintf(fqdev, len, "i(@%c.%s%s[current])", prefix, path, dev);
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else my_snprintf(fqdev, len, "i(@%c.%s%s[i])", prefix, path, dev);
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} else {
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if(vsource) my_snprintf(fqdev, len, "i(%s)", dev);
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else if(prefix == 'd') my_snprintf(fqdev, len, "i(@%s[id])", dev);
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else if(prefix == 'd' || prefix == 'm') my_snprintf(fqdev, len, "i(@%s[id])", dev);
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else if(prefix == 'i') my_snprintf(fqdev, len, "i(@%s[current])", dev);
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else my_snprintf(fqdev, len, "i(@%s[i])", dev);
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}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -51,4 +51,6 @@ T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance}
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T {@#3:net_name} 25 0.625 0 0 0.15 0.15 {layer=15 hide=instance}
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T {tcleval(vgs=[to_eng \{@#1:spice_get_voltage - @#2:spice_get_voltage \}]
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vds=[to_eng \{@#0:spice_get_voltage - @#2:spice_get_voltage \}])} -17.5 20 0 0 0.05 0.05 {layer=15 hide=instance}
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vds=[to_eng \{@#0:spice_get_voltage - @#2:spice_get_voltage \}])} 2.5 20 0 1 0.05 0.05 {layer=15 hide=instance}
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T {@spice_get_current} 25 20 0 0 0.15 0.15 {layer=17
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hide=instance}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -57,4 +57,6 @@ T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance}
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T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance}
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T {@#3:net_name} 25 1.25 0 0 0.15 0.15 {layer=15 hide=instance}
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T {tcleval(vgs=[to_eng \{@#1:spice_get_voltage - @#2:spice_get_voltage \}]
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vds=[to_eng \{@#0:spice_get_voltage - @#2:spice_get_voltage \}])} -17.5 20 0 0 0.05 0.05 {layer=15 hide=instance}
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vds=[to_eng \{@#0:spice_get_voltage - @#2:spice_get_voltage \}])} 2.5 20 0 1 0.05 0.05 {layer=15 hide=instance}
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T {@spice_get_current} 30 -30 0 0 0.15 0.15 {layer=17
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hide=instance}
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