diff --git a/src/token.c b/src/token.c index a8dc2beb..950cd994 100644 --- a/src/token.c +++ b/src/token.c @@ -4001,7 +4001,7 @@ const char *translate(int inst, const char* s) dbg(1, "prefix=%c, path=%s\n", prefix, path); vsource = (prefix == 'v') || (prefix == 'e'); if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s.%s)", prefix, path, instname, dev); - else if(prefix == 'd') + else if(prefix == 'd' || prefix == 'm') my_snprintf(fqdev, len, "i(@%c.%s%s.%s[id])", prefix, path, instname, dev); else if(prefix == 'i') my_snprintf(fqdev, len, "i(@%c.%s%s.%s[current])", prefix, path, instname, dev); @@ -4132,12 +4132,12 @@ const char *translate(int inst, const char* s) int vsource = (prefix == 'v') || (prefix == 'e'); if(path[0]) { if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s)", prefix, path, dev); - else if(prefix=='d') my_snprintf(fqdev, len, "i(@%c.%s%s[id])", prefix, path, dev); + else if(prefix=='d' || prefix == 'm') my_snprintf(fqdev, len, "i(@%c.%s%s[id])", prefix, path, dev); else if(prefix=='i') my_snprintf(fqdev, len, "i(@%c.%s%s[current])", prefix, path, dev); else my_snprintf(fqdev, len, "i(@%c.%s%s[i])", prefix, path, dev); } else { if(vsource) my_snprintf(fqdev, len, "i(%s)", dev); - else if(prefix == 'd') my_snprintf(fqdev, len, "i(@%s[id])", dev); + else if(prefix == 'd' || prefix == 'm') my_snprintf(fqdev, len, "i(@%s[id])", dev); else if(prefix == 'i') my_snprintf(fqdev, len, "i(@%s[current])", dev); else my_snprintf(fqdev, len, "i(@%s[i])", dev); } diff --git a/xschem_library/devices/nmos4.sym b/xschem_library/devices/nmos4.sym index 601cfd77..34b160cb 100644 --- a/xschem_library/devices/nmos4.sym +++ b/xschem_library/devices/nmos4.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.5 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -51,4 +51,6 @@ T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance} T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} T {@#3:net_name} 25 0.625 0 0 0.15 0.15 {layer=15 hide=instance} T {tcleval(vgs=[to_eng \{@#1:spice_get_voltage - @#2:spice_get_voltage \}] -vds=[to_eng \{@#0:spice_get_voltage - @#2:spice_get_voltage \}])} -17.5 20 0 0 0.05 0.05 {layer=15 hide=instance} +vds=[to_eng \{@#0:spice_get_voltage - @#2:spice_get_voltage \}])} 2.5 20 0 1 0.05 0.05 {layer=15 hide=instance} +T {@spice_get_current} 25 20 0 0 0.15 0.15 {layer=17 +hide=instance} diff --git a/xschem_library/devices/pmos4.sym b/xschem_library/devices/pmos4.sym index 03ba35e8..dd34fa6f 100644 --- a/xschem_library/devices/pmos4.sym +++ b/xschem_library/devices/pmos4.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.5 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -57,4 +57,6 @@ T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance} T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} T {@#3:net_name} 25 1.25 0 0 0.15 0.15 {layer=15 hide=instance} T {tcleval(vgs=[to_eng \{@#1:spice_get_voltage - @#2:spice_get_voltage \}] -vds=[to_eng \{@#0:spice_get_voltage - @#2:spice_get_voltage \}])} -17.5 20 0 0 0.05 0.05 {layer=15 hide=instance} +vds=[to_eng \{@#0:spice_get_voltage - @#2:spice_get_voltage \}])} 2.5 20 0 1 0.05 0.05 {layer=15 hide=instance} +T {@spice_get_current} 30 -30 0 0 0.15 0.15 {layer=17 +hide=instance}