removed some redundant code lines in netlist.c, updated xschemtest.tcl netlist hashes with new noconn.sym
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f8f7c4f230
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af153593e9
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@ -594,7 +594,6 @@ static void name_generics()
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/* name generic pins from attached labels */
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dbg(2, "name_generics(): naming generics from attached labels\n");
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if(for_netlist) for (i=0;i<instances; ++i) { /* ... assign node fields on all (non label) instances */
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if(inst[i].ptr<0) continue;
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if(skip_instance(i, 0, netlist_lvs_ignore)) continue;
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my_strdup(_ALLOC_ID_, &type,(inst[i].ptr+ xctx->sym)->type);
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if(type && !IS_LABEL_OR_PIN(type) ) {
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@ -845,8 +844,7 @@ int shorted_instance(int i, int lvs_ignore)
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static int skip_instance2(int i, int lvs_ignore, int mask)
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{
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int skip = 0;
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if(xctx->inst[i].ptr < 0) skip = 1;
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else if(xctx->inst[i].flags & mask) skip = 1;
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if(xctx->inst[i].flags & mask) skip = 1;
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else if(xctx->sym[xctx->inst[i].ptr].flags & mask) skip = 1;
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else if(lvs_ignore && (xctx->inst[i].flags & LVS_IGNORE)) skip = 1;
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else if(lvs_ignore && (xctx->sym[xctx->inst[i].ptr].flags & LVS_IGNORE)) skip = 1;
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@ -856,7 +854,8 @@ static int skip_instance2(int i, int lvs_ignore, int mask)
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int skip_instance(int i, int skip_short, int lvs_ignore)
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{
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int skip = 0;
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if(xctx->netlist_type == CAD_SPICE_NETLIST)
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if(xctx->inst[i].ptr < 0) skip = 1;
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else if(xctx->netlist_type == CAD_SPICE_NETLIST)
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skip = skip_instance2(i, lvs_ignore, (skip_short ? SPICE_SHORT : 0) | SPICE_IGNORE);
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else if(xctx->netlist_type == CAD_VERILOG_NETLIST)
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skip = skip_instance2(i, lvs_ignore, (skip_short ? VERILOG_SHORT : 0) | VERILOG_IGNORE);
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@ -1060,7 +1059,6 @@ static int name_nodes_of_pins_labels_and_propagate()
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print_erc = (xctx->netlist_count == 0 || startlevel < xctx->currsch) && for_netlist;
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for (i=0;i<instances; ++i) {
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/* name ipin opin label node fields from prop_ptr attributes */
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if(inst[i].ptr<0) continue;
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if(skip_instance(i, 0, netlist_lvs_ignore)) continue;
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my_strdup(_ALLOC_ID_, &type,(inst[i].ptr+ xctx->sym)->type);
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if(print_erc && (!inst[i].instname || !inst[i].instname[0]) &&
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@ -190,17 +190,17 @@ proc test_xschem_simulation {{f simulate_ff.sch}} {
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proc netlist_test {} {
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global netlist_dir
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foreach {f t h} {
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rom8k.sch spice 2260553850
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greycnt.sch verilog 2772589036
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rom8k.sch spice 1998661799
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greycnt.sch verilog 2899796185
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autozero_comp.sch spice 1181616733
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loading.sch vhdl 3300682141
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loading.sch vhdl 2975204502
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mos_power_ampli.sch spice 1986885043
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hierarchical_tedax.sch tedax 998070173
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hierarchical_tedax.sch tedax 280590167
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LCC_instances.sch spice 268038818
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pcb_test1.sch tedax 1925087189
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test_doublepin.sch spice 64707104
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simulate_ff.sch spice 1321596936
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test_symbolgen.sch spice 486085716
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test_doublepin.sch spice 894741562
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simulate_ff.sch spice 574849766
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test_symbolgen.sch spice 2593807370
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inst_sch_select.sch spice 801962545
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test_mosgen.sch spice 21996225
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} {
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