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tedax: do not generate __UNCONNECTED_PIN__%d names for unconnected instance pins in tedax netlist, do not highlight in red instances with unconected pins, still print ERC warning just in case designer forgot a connection

This commit is contained in:
Stefan Frederik 2022-01-11 14:40:43 +01:00
parent d273d5131e
commit aec7d02c4d
3 changed files with 6 additions and 8 deletions
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5
src/netlist.c
View File

@ -1002,9 +1002,8 @@ void prepare_netlist_structs(int for_netlist)
/* pin did not touch named pins or nets so we name it now */ /* pin did not touch named pins or nets so we name it now */
dbg(2, "prepare_netlist_structs(): naming the other pins\n"); dbg(2, "prepare_netlist_structs(): naming the other pins\n");
if (!touches) if (!touches) { /* pin does not touch any other instance pin with non NULL node[] field ...*/
{ if (touches_unnamed) /* ... but touches some other instance pin, so create unnamed net */
if (!(CAD_VHDL_NETLIST && !touches_unnamed))
{ {
expandlabel(get_tok_value( expandlabel(get_tok_value(
(inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0), &pin_mult); (inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0), &pin_mult);

4
src/token.c
View File

@ -1930,7 +1930,7 @@ void print_tedax_element(FILE *fd, int inst)
} }
if(!xctx->get_tok_size) my_strdup(501, &pinnumber, "--UNDEF--"); if(!xctx->get_tok_size) my_strdup(501, &pinnumber, "--UNDEF--");
tmp = net_name(inst,i, &multip, 0, 1); tmp = net_name(inst,i, &multip, 0, 1);
if(tmp && strcmp(tmp, "__UNCONNECTED_PIN__")) { if(tmp && !strstr(tmp, "__UNCONNECTED_PIN__")) {
fprintf(fd, "conn %s %s %s %s %d\n", fprintf(fd, "conn %s %s %s %s %d\n",
name, name,
tmp, tmp,
@ -2329,7 +2329,7 @@ const char *net_name(int i, int j, int *multip, int hash_prefix_unnamed_net, int
i, j, xctx->inst[i].instname ) ; i, j, xctx->inst[i].instname ) ;
statusmsg(errstr,2); statusmsg(errstr,2);
tcleval("show_infotext"); /* critical error: force ERC window showing */ tcleval("show_infotext"); /* critical error: force ERC window showing */
if(!xctx->netlist_count) { if(!xctx->netlist_count && xctx->netlist_type != CAD_TEDAX_NETLIST) {
xctx->inst[i].color = -PINLAYER; xctx->inst[i].color = -PINLAYER;
xctx->hilight_nets=1; xctx->hilight_nets=1;
} }

5
xschem_library/pcb/pcb_test1.sch
View File

@ -1,4 +1,4 @@
v {xschem version=2.9.9 file_version=1.2 } v {xschem version=3.0.0 file_version=1.2 }
G {} G {}
K {} K {}
V {} V {}
@ -18,7 +18,6 @@ N 480 -350 520 -350 {lab=B}
N 930 -440 970 -440 {lab=OUTPUT_Y} N 930 -440 970 -440 {lab=OUTPUT_Y}
N 310 -440 380 -440 {lab=INPUT_F} N 310 -440 380 -440 {lab=INPUT_F}
N 310 -480 380 -480 {lab=INPUT_E} N 310 -480 380 -480 {lab=INPUT_E}
N 480 -460 520 -460 {lab=A}
N 550 -190 670 -190 {lab=VCCFILT} N 550 -190 670 -190 {lab=VCCFILT}
N 590 -130 590 -110 {lab=ANALOG_GND} N 590 -130 590 -110 {lab=ANALOG_GND}
N 790 -190 940 -190 {lab=VCC5} N 790 -190 940 -190 {lab=VCC5}
@ -34,7 +33,6 @@ C {title.sym} 160 -30 0 0 {name=l2 author="Stefan"}
C {74ls00.sym} 420 -350 0 0 {name=U1:2 risedel=100 falldel=200} C {74ls00.sym} 420 -350 0 0 {name=U1:2 risedel=100 falldel=200}
C {74ls00.sym} 870 -440 0 0 {name=U1:1 risedel=100 falldel=200} C {74ls00.sym} 870 -440 0 0 {name=U1:1 risedel=100 falldel=200}
C {lab_pin.sym} 970 -440 0 1 {name=p0 lab=OUTPUT_Y} C {lab_pin.sym} 970 -440 0 1 {name=p0 lab=OUTPUT_Y}
C {capa.sym} 590 -160 0 0 {name=C0 m=1 value=100u device="electrolitic capacitor"}
C {74ls00.sym} 420 -460 0 0 {name=U1:4 risedel=100 falldel=200 C {74ls00.sym} 420 -460 0 0 {name=U1:4 risedel=100 falldel=200
url="http://www.engrcs.com/components/74LS00.pdf" url="http://www.engrcs.com/components/74LS00.pdf"
power=VCC5 power=VCC5
@ -91,3 +89,4 @@ C {lab_pin.sym} 40 -370 0 1 {name=l4 lab=INPUT_A verilog_type=reg}
C {lab_pin.sym} 40 -350 0 1 {name=l5 lab=INPUT_B verilog_type=reg} C {lab_pin.sym} 40 -350 0 1 {name=l5 lab=INPUT_B verilog_type=reg}
C {lab_pin.sym} 40 -410 0 1 {name=l6 lab=INPUT_E verilog_type=reg} C {lab_pin.sym} 40 -410 0 1 {name=l6 lab=INPUT_E verilog_type=reg}
C {lab_pin.sym} 40 -390 0 1 {name=l7 lab=INPUT_F verilog_type=reg} C {lab_pin.sym} 40 -390 0 1 {name=l7 lab=INPUT_F verilog_type=reg}
C {capa.sym} 590 -160 0 0 {name=C0 m=1 value=100u device="electrolitic capacitor"}