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@path expansion in translate(): remove path components above the level where raw file (if any) was loaded; added @spice_get_current in bsource.sym

This commit is contained in:
stefan schippers 2025-01-09 15:35:35 +01:00
parent c6a4e8b942
commit aa36cbb897
2 changed files with 13 additions and 1 deletions
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11
src/token.c
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@ -3739,6 +3739,15 @@ const char *translate(int inst, const char* s)
result_pos+=tmp; result_pos+=tmp;
} else if(strcmp(token,"@path")==0) { } else if(strcmp(token,"@path")==0) {
const char *path = xctx->sch_path[xctx->currsch] + 1; const char *path = xctx->sch_path[xctx->currsch] + 1;
int start_level = sch_waves_loaded(), skip = 0;
if(start_level == -1) start_level = 0;
/* skip path components that are above the level where raw file was loaded */
while(*path && skip < start_level) {
if(*path == '.') skip++;
++path;
}
tmp=strlen(path); tmp=strlen(path);
STR_ALLOC(&result, tmp + result_pos, &size); STR_ALLOC(&result, tmp + result_pos, &size);
memcpy(result+result_pos, path, tmp+1); memcpy(result+result_pos, path, tmp+1);
@ -4367,11 +4376,13 @@ const char *translate2(Lcc *lcc, int level, char* s)
} }
else if(strcmp(token,"@path")==0) { else if(strcmp(token,"@path")==0) {
char *path = NULL; char *path = NULL;
here(level);
my_strdup2(_ALLOC_ID_, &path, "@path@name\\."); my_strdup2(_ALLOC_ID_, &path, "@path@name\\.");
if(level > 1) { /* add parent LCC instance names (X1, Xinv etc) */ if(level > 1) { /* add parent LCC instance names (X1, Xinv etc) */
int i; int i;
for(i = 1; i <level; ++i) { for(i = 1; i <level; ++i) {
const char *instname = get_tok_value(lcc[i].prop_ptr, "name", 0); const char *instname = get_tok_value(lcc[i].prop_ptr, "name", 0);
dbg(0, "adding %s to %s\n", instname, path);
my_strcat(_ALLOC_ID_, &path, instname); my_strcat(_ALLOC_ID_, &path, instname);
my_strcat(_ALLOC_ID_, &path, "."); my_strcat(_ALLOC_ID_, &path, ".");
} }

3
xschem_library/devices/bsource.sym
View File

@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2 v {xschem version=3.4.6 file_version=1.2
* *
* This file is part of XSCHEM, * This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -39,3 +39,4 @@ T {@VAR
@FUNC} 20 0 0 0 0.2 0.2 {} @FUNC} 20 0 0 0 0.2 0.2 {}
T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15 hide=instance}
T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15 hide=instance} T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15 hide=instance}
T {@spice_get_current} -12.5 7.5 0 1 0.2 0.2 {layer=17}