comment typo, add one more example in inst_sch_select.sch

This commit is contained in:
stefan schippers 2024-03-08 00:08:48 +01:00
parent cf002964f3
commit 93722e8a21
3 changed files with 46 additions and 16 deletions

View File

@ -1957,7 +1957,7 @@ void get_additional_symbols(int what)
my_strdup2(_ALLOC_ID_, &sym, add_ext(rel_sym_path(sch), ".sym"));
}
/* if instance symbol has ignore_schematic set to ignore copy the symbol anyway, since
/* if instance symbol has default_schematic set to ignore copy the symbol anyway, since
* the base symbol will not be netlisted by *_block_netlist() */
found = ignore_schematic ? NULL : int_hash_lookup(&sym_table, sym, 0, XLOOKUP);
if(!found) {

View File

@ -0,0 +1,27 @@
.subckt comp3_pex2 PLUS MINUS OUT
** parasitic netlist
cparax1 net1 0 70f
cparax2 net2 0 70f
cparax3 net3 0 70f
cparax4 net4 0 70f
cparax5 net5 0 70f
cparaxout out 0 80f
M1 net1 GN1 0 0 nmos w=4u l=0.4u m=1
M2 GN1 GN1 0 0 nmos w=4u l=0.4u m=1
I0 VCC GN1 30u
M3 net2 MINUS net1 0 nmos w=1.5u l=0.2u m=1
M4 net3 PLUS net1 0 nmos w=1.5u l=0.2u m=1
M5 net2 net2 VCC VCC pmos w=6u l=0.3u m=1
M6 net3 net2 VCC VCC pmos w=6u l=0.3u m=1
M14 net4 net3 VCC VCC pmos w=6u l=0.3u m=1
.save v(gn1)
.save v(net2)
M7 net4 GN1 0 0 nmos w=4u l=0.4u m=1
M8 net5 net4 0 0 nmos w=1u l=0.4u m=1
M9 net5 net4 VCC VCC pmos w=2u l=0.4u m=1
M10 OUT net5 0 0 nmos w=1u l=0.4u m=1
M11 OUT net5 VCC VCC pmos w=2u l=0.4u m=1
M13 net4 net4 net5 0 nmos w=2u l=0.1u m=1
M12 net5 net5 net4 0 nmos w=2u l=0.1u m=1
C2 GN1 0 200f m=1
.ends

View File

@ -41,8 +41,9 @@ out2
out3
out4
out5
out6"
color="7 8 9 10 11 12"
out6
out7"
color="7 8 9 10 11 12 13"
dataset=-1
unitx=1
logx=0
@ -60,14 +61,15 @@ x1=-2.5e-09
x2=4.75e-08
divx=5
subdivx=1
node="plus
minus"
color="4 14"
dataset=-1
unitx=1
logx=0
logy=0
hilight_wave=-1}
hilight_wave=-1
color="4 7"
node="plus minus"}
T {Default instance:
Uses comp3.sch} 10 -1190 0 0 0.4 0.4 { layer=7}
T {Alternate instance:
@ -102,7 +104,7 @@ C {comp3.sym} 180 -870 0 0 {name=x2
schematic=comp3_parax.sch}
C {comp3.sym} 180 -600 0 0 {name=x3
schematic=comp3_pex
spice_sym_def=".subckt comp3_pex PLUS OUT MINUS
spice_sym_def=".subckt comp3_pex MINUS PLUS OUT
** parasitic netlist
cparax1 net1 0 20f
cparax2 net2 0 20f
@ -132,15 +134,15 @@ C2 GN1 0 200f m=1
verilog_sym_def="verilog stuff"
vhdl_sym_def="vhdl stuff"}
C {comp3.sym} 180 -290 0 0 {name=x10
schematic=comp3_pex
spice_sym_def=".include comp3_pex2.cir"
C {comp3.sym} 180 -290 0 0 {name=x4
schematic=comp3_pex2
spice_sym_def="tcleval(.include [abs_sym_path comp3_pex2.cir])"
verilog_sym_def="verilog stuff"
vhdl_sym_def="vhdl stuff"}
C {comp3.sym} 490 -730 0 0 {name=x4
C {comp3.sym} 490 -730 0 0 {name=x5
schematic=comp3_empty.sch}
C {comp3.sym} 490 -450 0 0 {name=x5
C {comp3.sym} 490 -450 0 0 {name=x6
schematic=comp3_file
spice_sym_def="tcleval(
[read_data_nonewline [abs_sym_path comp3_file.cir]]
@ -150,7 +152,7 @@ vhdl_sym_def="tcleval(
[read_data_nonewline [abs_sym_path comp3_file.cir]]
)"
tclcommand="textwindow [abs_sym_path comp3_file.cir]"}
C {comp3_read.sym} 490 -230 0 0 {name=x6
C {comp3_read.sym} 490 -230 0 0 {name=x7
tclcommand="textwindow [abs_sym_path comp3_read.cir]"}
C {lab_pin.sym} 240 -1080 0 1 {name=p2 lab=OUT1}
@ -177,9 +179,10 @@ tclcommand="xschem raw_read $netlist_dir/test_instance_schematic_selection.raw t
}
C {code_shown.sym} 140 -170 0 0 {name=COMMANDS only_toplevel=false value=".control
save all
tran 1n 50n
tran 0.05n 50n
write test_instance_schematic_selection.raw
.endc"}
.endc
"}
C {lab_pin.sym} 120 -1110 0 0 {name=p1 lab=PLUS}
C {lab_pin.sym} 430 -760 0 0 {name=p15 lab=PLUS}
C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version released on 2/22/06