comment typo, add one more example in inst_sch_select.sch
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cf002964f3
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@ -1957,7 +1957,7 @@ void get_additional_symbols(int what)
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my_strdup2(_ALLOC_ID_, &sym, add_ext(rel_sym_path(sch), ".sym"));
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}
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/* if instance symbol has ignore_schematic set to ignore copy the symbol anyway, since
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/* if instance symbol has default_schematic set to ignore copy the symbol anyway, since
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* the base symbol will not be netlisted by *_block_netlist() */
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found = ignore_schematic ? NULL : int_hash_lookup(&sym_table, sym, 0, XLOOKUP);
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if(!found) {
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@ -0,0 +1,27 @@
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.subckt comp3_pex2 PLUS MINUS OUT
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** parasitic netlist
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cparax1 net1 0 70f
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cparax2 net2 0 70f
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cparax3 net3 0 70f
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cparax4 net4 0 70f
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cparax5 net5 0 70f
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cparaxout out 0 80f
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M1 net1 GN1 0 0 nmos w=4u l=0.4u m=1
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M2 GN1 GN1 0 0 nmos w=4u l=0.4u m=1
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I0 VCC GN1 30u
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M3 net2 MINUS net1 0 nmos w=1.5u l=0.2u m=1
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M4 net3 PLUS net1 0 nmos w=1.5u l=0.2u m=1
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M5 net2 net2 VCC VCC pmos w=6u l=0.3u m=1
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M6 net3 net2 VCC VCC pmos w=6u l=0.3u m=1
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M14 net4 net3 VCC VCC pmos w=6u l=0.3u m=1
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.save v(gn1)
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.save v(net2)
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M7 net4 GN1 0 0 nmos w=4u l=0.4u m=1
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M8 net5 net4 0 0 nmos w=1u l=0.4u m=1
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M9 net5 net4 VCC VCC pmos w=2u l=0.4u m=1
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M10 OUT net5 0 0 nmos w=1u l=0.4u m=1
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M11 OUT net5 VCC VCC pmos w=2u l=0.4u m=1
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M13 net4 net4 net5 0 nmos w=2u l=0.1u m=1
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M12 net5 net5 net4 0 nmos w=2u l=0.1u m=1
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C2 GN1 0 200f m=1
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.ends
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@ -41,8 +41,9 @@ out2
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out3
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out4
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out5
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out6"
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color="7 8 9 10 11 12"
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out6
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out7"
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color="7 8 9 10 11 12 13"
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dataset=-1
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unitx=1
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logx=0
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@ -60,14 +61,15 @@ x1=-2.5e-09
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x2=4.75e-08
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divx=5
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subdivx=1
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node="plus
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minus"
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color="4 14"
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dataset=-1
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unitx=1
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logx=0
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logy=0
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hilight_wave=-1}
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hilight_wave=-1
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color="4 7"
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node="plus minus"}
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T {Default instance:
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Uses comp3.sch} 10 -1190 0 0 0.4 0.4 { layer=7}
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T {Alternate instance:
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@ -102,7 +104,7 @@ C {comp3.sym} 180 -870 0 0 {name=x2
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schematic=comp3_parax.sch}
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C {comp3.sym} 180 -600 0 0 {name=x3
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schematic=comp3_pex
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spice_sym_def=".subckt comp3_pex PLUS OUT MINUS
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spice_sym_def=".subckt comp3_pex MINUS PLUS OUT
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** parasitic netlist
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cparax1 net1 0 20f
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cparax2 net2 0 20f
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@ -132,15 +134,15 @@ C2 GN1 0 200f m=1
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verilog_sym_def="verilog stuff"
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vhdl_sym_def="vhdl stuff"}
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C {comp3.sym} 180 -290 0 0 {name=x10
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schematic=comp3_pex
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spice_sym_def=".include comp3_pex2.cir"
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C {comp3.sym} 180 -290 0 0 {name=x4
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schematic=comp3_pex2
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spice_sym_def="tcleval(.include [abs_sym_path comp3_pex2.cir])"
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verilog_sym_def="verilog stuff"
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vhdl_sym_def="vhdl stuff"}
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C {comp3.sym} 490 -730 0 0 {name=x4
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C {comp3.sym} 490 -730 0 0 {name=x5
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schematic=comp3_empty.sch}
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C {comp3.sym} 490 -450 0 0 {name=x5
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C {comp3.sym} 490 -450 0 0 {name=x6
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schematic=comp3_file
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spice_sym_def="tcleval(
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[read_data_nonewline [abs_sym_path comp3_file.cir]]
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@ -150,7 +152,7 @@ vhdl_sym_def="tcleval(
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[read_data_nonewline [abs_sym_path comp3_file.cir]]
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)"
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tclcommand="textwindow [abs_sym_path comp3_file.cir]"}
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C {comp3_read.sym} 490 -230 0 0 {name=x6
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C {comp3_read.sym} 490 -230 0 0 {name=x7
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tclcommand="textwindow [abs_sym_path comp3_read.cir]"}
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C {lab_pin.sym} 240 -1080 0 1 {name=p2 lab=OUT1}
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@ -177,9 +179,10 @@ tclcommand="xschem raw_read $netlist_dir/test_instance_schematic_selection.raw t
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}
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C {code_shown.sym} 140 -170 0 0 {name=COMMANDS only_toplevel=false value=".control
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save all
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tran 1n 50n
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tran 0.05n 50n
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write test_instance_schematic_selection.raw
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.endc"}
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.endc
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"}
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C {lab_pin.sym} 120 -1110 0 0 {name=p1 lab=PLUS}
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C {lab_pin.sym} 430 -760 0 0 {name=p15 lab=PLUS}
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C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version released on 2/22/06
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