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fix wrong unselection of text objects after changing text layer (delete_only_rect_line_arc_poly() erroneously setting xctx->lastsel to 0)

This commit is contained in:
stefan schippers 2024-03-07 23:38:00 +01:00
parent 132d335757
commit cf002964f3
2 changed files with 80 additions and 63 deletions
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6
src/select.c
View File

@ -483,7 +483,10 @@ static void del_rect_line_arc_poly()
}
xctx->polygons[c] -= j;
}
if(deleted) set_modify(1);
if(deleted) {
set_modify(1);
xctx->need_reb_sel_arr = 1;
}
}
int delete_wires(int selected_flag)
@ -607,7 +610,6 @@ void delete(int to_push_undo)
void delete_only_rect_line_arc_poly(void)
{
del_rect_line_arc_poly();
xctx->lastsel = 0;
draw();
xctx->ui_state &= ~SELECTION;
set_first_sel(0, -1, 0);

137
xschem_library/inst_sch_select/inst_sch_select.sch
View File

@ -69,38 +69,38 @@ logx=0
logy=0
hilight_wave=-1}
T {Default instance:
Uses comp3.sch} 10 -930 0 0 0.4 0.4 { layer=9}
Uses comp3.sch} 10 -1190 0 0 0.4 0.4 { layer=7}
T {Alternate instance:
Uses comp3_parax.sch} 10 -720 0 0 0.4 0.4 { layer=10}
Uses comp3_parax.sch} 10 -980 0 0 0.4 0.4 { layer=8}
T {Alternate instance:
Uses comp3_pex
contained in attribute
spice_sym_def
No schematic used} 10 -520 0 0 0.4 0.4 { layer=11}
No schematic used} 10 -780 0 0 0.4 0.4 { layer=9}
T {Alternate instance:
Uses comp3_empty.sch
netlist embedded in global
spice schematic attribute} 340 -920 0 0 0.4 0.4 { layer=12}
spice schematic attribute} 340 -920 0 0 0.4 0.4 { layer=11}
T {Alternate instance:
Uses spice_sym_def to read in
file comp3_file.cir
no schematic used} 340 -620 0 0 0.4 0.4 { layer=13}
no schematic used} 340 -620 0 0 0.4 0.4 { layer=12}
T {The same symbol is simulated with 5 different implementations
using instance 'schematic' and 'spice_sym_def' attributes} 190 -1040 0 0 0.6 0.6 { layer=4 slant=oblique}
T {Instance based implementation selection.} 250 -1100 0 0 0.8 0.8 {}
using instance 'schematic' and 'spice_sym_def' attributes} 510 -1050 0 0 0.6 0.6 { layer=4 slant=oblique}
T {Instance based implementation selection.} 570 -1110 0 0 0.8 0.8 {}
T {comp3_read.sym:
symbol has "spice_sym_def"
attribute and reads in a file} 340 -360 0 0 0.4 0.4 { layer=14}
C {comp3.sym} 180 -820 0 0 {name=x1}
C {lab_pin.sym} 120 -850 0 0 {name=p1 lab=PLUS}
C {lab_pin.sym} 240 -820 0 1 {name=p2 lab=OUT1}
C {lab_pin.sym} 120 -790 0 0 {name=p3 lab=MINUS}
C {comp3.sym} 180 -610 0 0 {name=x2
attribute and reads in a file} 340 -360 0 0 0.4 0.4 { layer=13}
T {Alternate instance:
Uses comp3_pex2
referenced by a
.include comp3_pex2.cir
in spice_sym_def
No schematic used} 10 -500 0 0 0.4 0.4 { layer=10}
C {comp3.sym} 180 -1080 0 0 {name=x1}
C {comp3.sym} 180 -870 0 0 {name=x2
schematic=comp3_parax.sch}
C {lab_pin.sym} 120 -640 0 0 {name=p4 lab=PLUS}
C {lab_pin.sym} 240 -610 0 1 {name=p5 lab=OUT2}
C {lab_pin.sym} 120 -580 0 0 {name=p6 lab=MINUS}
C {comp3.sym} 180 -340 0 0 {name=x3
C {comp3.sym} 180 -600 0 0 {name=x3
schematic=comp3_pex
spice_sym_def=".subckt comp3_pex PLUS OUT MINUS
** parasitic netlist
@ -132,9 +132,56 @@ C2 GN1 0 200f m=1
verilog_sym_def="verilog stuff"
vhdl_sym_def="vhdl stuff"}
C {lab_pin.sym} 120 -370 0 0 {name=p7 lab=PLUS}
C {lab_pin.sym} 240 -340 0 1 {name=p8 lab=OUT3}
C {lab_pin.sym} 120 -310 0 0 {name=p9 lab=MINUS}
C {comp3.sym} 180 -290 0 0 {name=x10
schematic=comp3_pex
spice_sym_def=".include comp3_pex2.cir"
verilog_sym_def="verilog stuff"
vhdl_sym_def="vhdl stuff"}
C {comp3.sym} 490 -730 0 0 {name=x4
schematic=comp3_empty.sch}
C {comp3.sym} 490 -450 0 0 {name=x5
schematic=comp3_file
spice_sym_def="tcleval(
[read_data_nonewline [abs_sym_path comp3_file.cir]]
)"
vhdl_sym_def="tcleval(
[read_data_nonewline [abs_sym_path comp3_file.cir]]
)"
tclcommand="textwindow [abs_sym_path comp3_file.cir]"}
C {comp3_read.sym} 490 -230 0 0 {name=x6
tclcommand="textwindow [abs_sym_path comp3_read.cir]"}
C {lab_pin.sym} 240 -1080 0 1 {name=p2 lab=OUT1}
C {lab_pin.sym} 240 -870 0 1 {name=p5 lab=OUT2}
C {lab_pin.sym} 240 -600 0 1 {name=p8 lab=OUT3}
C {lab_pin.sym} 240 -290 0 1 {name=p35 lab=OUT4}
C {lab_pin.sym} 550 -730 0 1 {name=p16 lab=OUT5}
C {lab_pin.sym} 550 -450 0 1 {name=p19 lab=OUT6}
C {lab_pin.sym} 550 -230 0 1 {name=p23 lab=OUT7}
C {lab_pin.sym} 120 -840 0 0 {name=p6 lab=MINUS}
C {lab_pin.sym} 700 -90 0 0 {name=p10 lab=0}
C {vsource.sym} 820 -120 0 0 {name=V2 value=1
savecurrent=true}
C {lab_pin.sym} 820 -150 0 0 {name=p11 lab=MINUS}
C {lab_pin.sym} 820 -90 0 0 {name=p12 lab=0}
C {vsource.sym} 970 -120 0 0 {name=V3 value="pwl 0 0 10n 0 20n 2 30n 2 40n 0"
savecurrent=true}
C {lab_pin.sym} 970 -150 0 0 {name=p13 lab=PLUS}
C {lab_pin.sym} 970 -90 0 0 {name=p14 lab=0}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {launcher.sym} 820 -190 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/test_instance_schematic_selection.raw tran"
}
C {code_shown.sym} 140 -170 0 0 {name=COMMANDS only_toplevel=false value=".control
save all
tran 1n 50n
write test_instance_schematic_selection.raw
.endc"}
C {lab_pin.sym} 120 -1110 0 0 {name=p1 lab=PLUS}
C {lab_pin.sym} 430 -760 0 0 {name=p15 lab=PLUS}
C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version released on 2/22/06
* PTM 65nm NMOS
@ -261,49 +308,17 @@ C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version r
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
"}
C {lab_pin.sym} 430 -700 0 0 {name=p17 lab=MINUS}
C {lab_pin.sym} 120 -900 0 0 {name=p4 lab=PLUS}
C {lab_pin.sym} 430 -480 0 0 {name=p18 lab=PLUS}
C {vsource.sym} 700 -120 0 0 {name=V1 value=2
savecurrent=true}
C {lab_pin.sym} 700 -150 0 0 {name=p21 lab=VCC}
C {lab_pin.sym} 700 -90 0 0 {name=p10 lab=0}
C {vsource.sym} 820 -120 0 0 {name=V2 value=1
savecurrent=true}
C {lab_pin.sym} 820 -150 0 0 {name=p11 lab=MINUS}
C {lab_pin.sym} 820 -90 0 0 {name=p12 lab=0}
C {vsource.sym} 970 -120 0 0 {name=V3 value="pwl 0 0 10n 0 20n 2 30n 2 40n 0"
savecurrent=true}
C {lab_pin.sym} 970 -150 0 0 {name=p13 lab=PLUS}
C {lab_pin.sym} 970 -90 0 0 {name=p14 lab=0}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {launcher.sym} 820 -190 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/test_instance_schematic_selection.raw tran"
}
C {code_shown.sym} 140 -170 0 0 {name=COMMANDS only_toplevel=false value=".control
save all
tran 1n 50n
write test_instance_schematic_selection.raw
.endc"}
C {comp3.sym} 490 -730 0 0 {name=x4
schematic=comp3_empty.sch}
C {lab_pin.sym} 430 -760 0 0 {name=p15 lab=PLUS}
C {lab_pin.sym} 550 -730 0 1 {name=p16 lab=OUT4}
C {lab_pin.sym} 430 -700 0 0 {name=p17 lab=MINUS}
C {comp3.sym} 490 -450 0 0 {name=x5
schematic=comp3_file
spice_sym_def="tcleval(
[read_data_nonewline [abs_sym_path comp3_file.cir]]
)"
vhdl_sym_def="tcleval(
[read_data_nonewline [abs_sym_path comp3_file.cir]]
)"
tclcommand="textwindow [abs_sym_path comp3_file.cir]"}
C {lab_pin.sym} 430 -480 0 0 {name=p18 lab=PLUS}
C {lab_pin.sym} 550 -450 0 1 {name=p19 lab=OUT5}
C {lab_pin.sym} 430 -420 0 0 {name=p20 lab=MINUS}
C {comp3_read.sym} 490 -230 0 0 {name=x6
tclcommand="textwindow [abs_sym_path comp3_read.cir]"}
C {lab_pin.sym} 120 -630 0 0 {name=p7 lab=PLUS}
C {lab_pin.sym} 430 -260 0 0 {name=p22 lab=PLUS}
C {lab_pin.sym} 550 -230 0 1 {name=p23 lab=OUT6}
C {lab_pin.sym} 700 -150 0 0 {name=p21 lab=VCC}
C {lab_pin.sym} 430 -200 0 0 {name=p24 lab=MINUS}
C {lab_pin.sym} 120 -1050 0 0 {name=p3 lab=MINUS}
C {lab_pin.sym} 120 -320 0 0 {name=p34 lab=PLUS}
C {lab_pin.sym} 120 -570 0 0 {name=p9 lab=MINUS}
C {lab_pin.sym} 120 -260 0 0 {name=p36 lab=MINUS}