doc update

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stefan schippers 2023-03-04 11:09:54 +01:00
parent 99a3e70e94
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4 changed files with 143 additions and 436 deletions

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@ -464,7 +464,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
</pre>
<img src="developer_info_06.png"><br>
<br>
<h1>XSCHEM COMMANDS REFERENCE DOCUMENTATION</h1><br>
<h1>XSCHEM <a id="cmdref">COMMAND REFERENCE</a> DOCUMENTATION</h1><br>
<p>
The following are xschem specific tcl commands.
All commands are prefixed by the <kbd>xschem</kbd> keyword.
@ -476,164 +476,162 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
<br>
<ul> <!-- Following list items generated in xschem src dir with:
./extract_scheduler_cmd_help.awk scheduler.c > ~/xxx
Include ~/xxx here.
Include ~/xxx here between <ul> and </ul>
-->
<li><kbd> abort_operation</kbd></li><pre>
Resets UI state, unselect all and abort any pending operation </pre>
<li><kbd> add_symbol_pin</kbd></li><pre>
Start a GUI placement of a symbol pin </pre>
<li><kbd> add_graph</kbd></li><pre>
Start a GUI placement of a graph object </pre>
<li><kbd> add_png</kbd></li><pre>
Ask user to choose a png file and start a GUI placement of the image </pre>
<li><kbd> align</kbd></li><pre>
Align currently selected objects to current snap setting </pre>
<li><kbd> annotate_op [raw_file]</kbd></li><pre>
Annotate operating point data into current schematic.
use &lt;schematic name&gt;.raw or use supplied argument as raw file to open
look for operating point data and annotate voltages/currents into schematic </pre>
<li><kbd> arc</kbd></li><pre>
Start a GUI placement of an arc.
User should click 3 unaligned points to define the arc </pre>
<li><kbd> attach_labels</kbd></li><pre>
Attach net labels to selected component(s) instance(s) </pre>
<li><kbd> bbox begin|end</kbd></li><pre>
Start/end bounding box calculation: parameter is either 'begin' or 'end' </pre>
<li><kbd> break_wires</kbd></li><pre>
Break wires at selected instance pins </pre>
<li><kbd> build_colors</kbd></li><pre>
Rebuild color palette using values of tcl vars dim_value and dim_bg </pre>
<li><kbd> callback winpath event mx my key button aux state</kbd></li><pre>
Invoke the callback event dispatcher with a software event </pre>
<li><kbd> case_insensitive 1|0</kbd></li><pre>
Set case insensitive symbol lookup. Use only on case insensitive filesystems </pre>
<li><kbd> check_symbols</kbd></li><pre>
List all used symbols in current schematic and warn if some symbol is newer </pre>
<li><kbd> check_unique_names [1|0]</kbd></li><pre>
Check if all instances have a unique refdes (name attribute in xschem),
highlight such instances. If second parameter is '1' rename duplicates </pre>
<li><kbd> circle</kbd></li><pre>
Start a GUI placement of a circle.
User should click 3 unaligned points to define the circle </pre>
<li><kbd> clear [force] [symbol|schematic]</kbd></li><pre>
Clear current schematic window. Resets hierarchy level. Remove symbols
the 'force' parameter will not ask to save existing modified schematic.
the 'schematic' or 'symbol' parameter specifies to default to a schematic
or symbol window (default: schematic) </pre>
<li><kbd> clear_drawing</kbd></li><pre>
Clears drawing but does not purge symbols </pre>
<li><kbd> color_dim value</kbd></li><pre>
Dim colors or brite colors depending on value parameter: -5 &lt;= value &lt;= 5 </pre>
<li><kbd> compare_schematics [sch_file]</kbd></li><pre>
Compare currently loaded schematic with another 'sch_file' schematic.
if no file is given prompt user to choose one </pre>
<li><kbd> connected_nets [1|0]</kbd></li><pre>
Selected nets connected to currently selected net or net label/pin.
if '1' argument is given, stop at wire junctions </pre>
<li><kbd> copy</kbd></li><pre>
Copy selection to clipboard </pre>
<li><kbd> copy_objects</kbd></li><pre>
Start a GUI copy operation </pre>
<li><kbd> count_items string separator quoting_chars</kbd></li><pre>
Debug command </pre>
<li><kbd> Create_plot_cmd</kbd></li><pre>
Create an xplot file in netlist/simulation directory with the list of highlighted nodes
in a format the selected waveform viewer understands (bespice, gaw, ngspice) </pre>
<li><kbd> cut</kbd></li><pre>
Cut selection to clipboard </pre>
<li><kbd> debug n</kbd></li><pre>
Set xschem in debug mode.'n' is the debug level (0=no debug). Higher levels yield more debug info.</pre>
<li><kbd> delete</kbd></li><pre>
Delete selection </pre>
<li><kbd> delete_files</kbd></li><pre>
Bring up a file selector the user can use to delete files </pre>
<li><kbd> descend [n]</kbd></li><pre>
Descend into selected component instance. Optional number 'n' specifies the
instance number to descend into for vector instances (default: 0). </pre>
<li><kbd> descend_symbol</kbd></li><pre>
Descend into the symbol view of selected component instance </pre>
<li><kbd> display_hilights</kbd></li><pre>
Print a list of highlighted objects (nets, net labels/pins, instances) </pre>
<li><kbd> draw_graph [n] [flags]</kbd></li><pre>
Redraw graph rectangle number 'n'. If the optional 'flags' integer is given it will be used as the
flags bitmask to use while drawing (can be used to restrict what to redraw) </pre>
<li><kbd> edit_file</kbd></li><pre>
Edit xschem file of current schematic if nothing is selected.
Edit .sym file if a component is selected. </pre>
<li><kbd> edit_prop</kbd></li><pre>
Edit global schematic/symbol attributes or attributes of currently selected instances </pre>
<li><kbd> edit_prop</kbd></li><pre>
Edit global schematic/symbol attributes or attributes of currently selected instances
using a text editor (defined in tcl 'editor' variable) </pre>
<li><kbd> embed_rawfile raw_file</kbd></li><pre>
Embed base 64 encoded 'raw_file' into currently selected element as a 'spice_data'
attribute. </pre>
<li><kbd> enable_layers</kbd></li><pre>
Enable/disable layers depending on tcl array variable enable_layer() </pre>
<li><kbd> exit</kbd></li><pre>
Exit the program, ask for confirm if current file modified. </pre>
<li><kbd> expandlabel lab</kbd></li><pre>
Expand vectored labels/instance names:
xschem expandlabel {2*A[3:0]} --&gt; A[3],A[2],A[1],A[0],A[3],A[2],A[1],A[0] 8
last field is the number of bits
since [ and ] are TCL special characters argument must be quoted with { and } </pre>
<li><kbd> find_nth string sep n</kbd></li><pre>
Find n-th field string separated by characters in sep. 1st field is in position 1
xschem find_nth {aaa,bbb,ccc,ddd} {,} 2 --&gt; bbb </pre>
<li><kbd> flip</kbd></li><pre>
Flip selection horizontally </pre>
<li><kbd> flip_in_place</kbd></li><pre>
Flip selection horizontally, each object around its center </pre>
<li><kbd> fullscreen</kbd></li><pre>
Toggle fullscreen modes: fullscreen with menu &amp; status, fullscreen, normal </pre>
<li><kbd> get var</kbd></li><pre>
Get C variable/constant 'var' </pre>
<ul>
<li><kbd> backlayer </kbd> number of background layer </li>
<li><kbd> bbox_hilighted </kbd> bounding box of highlinhted objects </li>
<li><kbd> bbox_selected </kbd> bounding box of selected objects </li>
<li><kbd> cadlayers </kbd> number of layers </li>
<li><kbd> case_insensitive </kbd> case_insensitive symbol matching </li>
<li><kbd> color_ps </kbd> color postscript flag </li>
<li><kbd> current_dirname </kbd> directory name of current design </li>
<li><kbd> current_name </kbd> name of current design (no library path) </li>
<li><kbd> current_win_path </kbd> path of current tab/window (.drw, .x1.drw, ...) </li>
<li><kbd> currsch </kbd> hierarchy level of current schematic (start at 0) </li>
<li><kbd> debug_var </kbd> debug level (0 = no debug, 1, 2, 3,...) </li>
<li><kbd> draw_window </kbd> direct draw into window </li>
<li><kbd> format </kbd> alternate format attribute to use in netlist (or NULL) </li>
<li><kbd> graph_lastsel </kbd> number of last graph that was clicked </li>
<li><kbd> gridlayer </kbd> layer number for grid </li>
<li><kbd> help </kbd> command help </li>
<li><kbd> header_text </kbd> header metadata (license info etc) present in schematic </li>
<li><kbd> instances </kbd> number of instances in schematic </li>
<li><kbd> lastsel </kbd> number of selected objects </li>
<li><kbd> line_width </kbd> get line width </li>
<li><kbd> netlist_name </kbd> netlist name if set. If 'fallback' given get default name </li>
<li><kbd> netlist_type </kbd> get current netlist type (spice/vhdl/verilog/tedax) </li>
<li><kbd> no_draw </kbd> disable drawing </li>
<li><kbd> ntabs </kbd> get number of additional tabs (0 = only one tab) </li>
<li><kbd> pinlayer </kbd> layer number for pins </li>
<li><kbd> rectcolor </kbd> current layer number </li>
<li><kbd> sellayer </kbd> layer number for selection </li>
<li><kbd> semaphore </kbd> used for debug </li>
<li><kbd> schname </kbd> get full path of current sch. if 'n' given get sch of level 'n' </li>
<li><kbd> sch_path </kbd> get hierarchy path. if 'n' given get hierpath of level 'n' </li>
<li><kbd> sch_to_compare </kbd> if set return schematic current design is compared with </li>
<li><kbd> temp_dir </kbd> get windows temporary dir </li>
<li><kbd> text_svg </kbd> return 1 if using &lt;text&gt; elements in svg export </li>
<li><kbd> textlayer </kbd> layer number for texts </li>
<li><kbd> top_path </kbd> get top hier path of current window (always "") for tabbed if </li>
<li><kbd> topwindow </kbd> same as top_path but main window returned as "." </li>
<li><kbd> version </kbd> return xschem version </li>
<li><kbd> wirelayer </kbd> layer used for wires </li>
<li><kbd> xorigin </kbd> x coordinate of origin </li>
<li><kbd> yorigin </kbd> y coordinate of origin </li>
<li><kbd> zoom </kbd> zoom level </li>
</ul>
<li><kbd> getprop instance inst </kbd></li><pre>
Get the full attribute string of 'inst'
@ -669,92 +667,70 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
('inst' can be an instance name or instance number)
('pin' can be a pin name or pin number)</pre>
<li><kbd> get_tok str tok [with_quotes]</kbd></li><pre>
get value of token 'tok' in string 'str'
'with_quotes' (default:0) is an integer passed to get_tok_value() </pre>
<li><kbd> get_tok_size</kbd></li><pre>
Get length of last looked up attribute name (not its value)
if returned value is 0 it means that last searched attribute did not exist </pre>
<li><kbd> globals</kbd></li><pre>
Return various global variables used in the program </pre>
<li><kbd> go_back</kbd></li><pre>
Go up one level (pop) in hierarchy </pre>
<li><kbd> hash_file file [skip_path_lines]</kbd></li><pre>
Do a simple hash of 'file'
'skip_path_lines' is an integer (default: 0) passed to hash_file() </pre>
<li><kbd> hash_string str</kbd></li><pre>
Do a simple hashing of string 'str' </pre>
<li><kbd> help</kbd></li><pre>
Print command help </pre>
<li><kbd> hier_psprint [file]</kbd></li><pre>
Hierarchical postscript / pdf print
if 'file' is not given show a fileselector dialog box </pre>
<li><kbd> hilight [drill]</kbd></li><pre>
Highlight selected element/pins/labels/nets
if 'drill' is given propagate net highlights through conducting elements
(elements that have the 'propag' attribute on pins ) </pre>
<li><kbd> hilight_instname inst</kbd></li><pre>
Highlight instance 'inst'
'inst' can be an instance name or number </pre>
<li><kbd> hilight_netname net</kbd></li><pre>
Highlight net name 'net' </pre>
<li><kbd> instance sym_name x y rot flip [prop] [first_call]</kbd></li><pre>
Place a new instance of symbol 'sym_name' at position x,y,
rotation and flip set to 'rot', 'flip'
if 'prop' is given it is the new instance attribute string (default: symbol template string)
if 'first_call' is given it must be 1 on first call and zero on following calls
It is used only for efficiency reasons if placing multiple instances </pre>
<li><kbd> instance_bbox inst</kbd></li><pre>
return instance and symbol bounding boxes
'inst' can be an instance name or number </pre>
<li><kbd> instance_net inst pin</kbd></li><pre>
Return the name of the net attached to pin 'pin' of instance 'inst'
Example: xschem instance_net x3 MINUS --&gt; REF </pre>
<li><kbd> instance_nodemap inst</kbd></li><pre>
Return the instance name followed by a list of 'pin net' associations
example: xschem instance_nodemap x3
--&gt; x3 PLUS LED OUT LEVEL MINUS REF
instance x3 pin PLUS is attached to net LED, pin OUT to net LEVEL and so on... </pre>
<li><kbd> instance_pin_coord inst attr value</kbd></li><pre>
Return the name and coordinates of pin with attribute 'attr' set to 'value' of instance 'inst'
'inst can be an instance name or a number
Example: xschem instance_pin_coord x3 name MINUS --&gt; {MINUS} 600 -840 </pre>
<li><kbd> instance_pins inst</kbd></li><pre>
Return list of pins of instance 'inst'
'inst can be an instance name or a number </pre>
<li><kbd> instance_pos inst</kbd></li><pre>
Get number (position) of instance name 'inst' </pre>
<li><kbd> instances_to_net net</kbd></li><pre>
Return list of instances names and pins attached to net 'net'
Example: xschem instances_to_net PANEL
--&gt; { {Vsw} {plus} {580} {-560} } { {p2} {p} {660} {-440} } { {Vpanel1} {minus} {600} {-440} } </pre>
<li><kbd> line x1 y1 x2 y2 [pos]</kbd></li><pre>
Place a line on current layer (rectcolor)
if integer number 'pos' is given place lien at indicated position in the line array. </pre>
<li><kbd> line_width n</kbd></li><pre>
set line width to floating point number 'n' </pre>
<li><kbd> list_hierarchy</kbd></li><pre>
List all schematics at or below current hierarchy with modification times.
Example: xschem list_hiearchy
@ -763,31 +739,25 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
20230211_010031 {/home/schippes/xschem-repo/trunk/xschem_library/ngspice/pv_ngspice.sch}
20221011_175308 {/home/schippes/xschem-repo/trunk/xschem_library/ngspice/diode_ngspice.sch}
20221014_091945 {/home/schippes/xschem-repo/trunk/xschem_library/ngspice/comp_ngspice.sch}</pre>
<li><kbd> list_hilights [sep]</kbd></li><pre>
Sorted list of highlight nets, separated by character 'sep' (default: space) </pre>
<li><kbd> list_tokens str with_quotes</kbd></li><pre>
List tokens in string 'str'
with_quotes:
0: eat non escaped quotes (")
1: return unescaped quotes as part of the token value if they are present
2: eat backslashes </pre>
<li><kbd> load f [symbol|force|noundoreset|nofullzoom]</kbd></li><pre>
Load a new file 'f'.
'force': do not ask to save modified file or warn if opening an already open file
'noundoreset': do not reset the undo history
'symbol': do not load symbols (used if loading a symbol instead of a schematic)
'nofullzoom': do not do a fll zoom on new schematic.</pre>
<li><kbd> load_new_window [f]</kbd></li><pre>
Load schematic in a new tab/window. If 'f' not given prompt user </pre>
<li><kbd> log f</kbd></li><pre>
if 'f' is given output stderr messages to file 'f'
if 'f' is not given and a file log is open, close log file and resume logging to stderr </pre>
<li><kbd> logic_set n num</kbd></li><pre>
Set selected nets, net labels or pins to logic level 'n' 'num' times.
'n':
@ -797,7 +767,6 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
3 set to logic value Z
-1 toggle logic valie (1-&gt;0, 0-&gt;1)
the 'num' parameter is essentially useful only with 'toggle' (-1) value</pre>
<li><kbd> logic_set n num</kbd></li><pre>
Set selected nets, net labels or pins to logic level 'n' 'num' times.
'n':
@ -807,35 +776,27 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
3 set to logic value Z
-1 toggle logic valie (1-&gt;0, 0-&gt;1)
the 'num' parameter is essentially useful only with 'toggle' (-1) value</pre>
<li><kbd> make_sch_from_sel </kbd></li><pre>
create an LCC instance from selection and place it instead of selection
also ask if a symbol (.sym) file needs to be created </pre>
<li><kbd> make_symbol</kbd></li><pre>
From current schematic (circuit.sch) create a symbol (circuit.sym)
using ipin.sym, opin.sym, iopin.sym in schematic
to deduce symbol interface pins. </pre>
<li><kbd> merge [f]</kbd></li><pre>
Merge another file. if 'f' not given prompt user. </pre>
<li><kbd> move_objects [dx dy]</kbd></li><pre>
Start a move operation on selection and let user terminate the operation in the GUI
if dx and dy are given move by that amount. </pre>
<li><kbd> net_label [type]</kbd></li><pre>
Place a new net label
'type': 1: place a 'lab_pin.sym' label
0: place a 'lab_wire.sym' label
User should complete the placement in the GUI. </pre>
<li><kbd> net_pin_mismatch</kbd></li><pre>
Highlight nets attached to selected symbols with a different name than symbol pin </pre>
<li><kbd> netlist</kbd></li><pre>
do a netlist of current schematic in currently defined netlist format </pre>
<li><kbd> new_schematic create|destroy|destroy_all|switch_win winpath file</kbd></li><pre>
Open/destroy a new tab or window
create: create new empty window or with 'file' loaded if 'file' given.
@ -847,53 +808,40 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
switch_tab: switch context to specified 'winpath' tab
Main window/tab has winpath set to .drw,
Additional windows/tabs have winpath set to .x1.drw, .x2.drw and so on...</pre>
<li><kbd> new_symbol_window [f]</kbd></li><pre>
Start a new xschem process for a symbol.
If 'f' is given load specified symbol. </pre>
<li><kbd> new_window [f]</kbd></li><pre>
Start a new xschem process for a schematic.
If 'f' is given load specified schematic. </pre>
<li><kbd> only_probes</kbd></li><pre>
dim schematic to better show highlights </pre>
<li><kbd> origin x y [zoom]</kbd></li><pre>
Move origin to 'x, y', optionally changing zoom level to 'zoom' </pre>
<li><kbd> parse_cmd</kbd></li><pre>
debug command to test parse_cmd_string()
splits a command string into argv-like arguments
return # of args in *argc
argv[*argc] is always set to NULL </pre>
<li><kbd> parselabel str</kbd></li><pre>
Debug command to test vector net syntax parser </pre>
<li><kbd> paste [x y]</kbd></li><pre>
Paste clipboard. If 'x y' not given user should complete placement in the GUI </pre>
<li><kbd> pinlist inst</kbd></li><pre>
List all pins of instance 'inst'
Example: xschem pinlist x3
--&gt;
{ {0} {name=PLUS dir=in } } { {1} {name=OUT dir=out } } { {2} {name=MINUS dir=in } }</pre>
<li><kbd> place_symbol [sym_name] [prop]</kbd></li><pre>
Start a GUI placement operation of specified 'sym_name' symbol.
If 'sym_name' not given prompt user
'prop' is the attribute string of the symbol. If not given take from symbol template attribute.</pre>
<li><kbd> place_text </kbd></li><pre>
Start a GUI placement of a text object </pre>
<li><kbd> polygon</kbd></li><pre>
Start a GUI placement of a polygon </pre>
<li><kbd> preview_window create|draw|destroy [winpath] [file]</kbd></li><pre>
used in fileselector to show a schematic preview.</pre>
<li><kbd> print png|svg|ps|pdf img_file img_x img_y [x1 y1 x2 y2]</kbd></li><pre>
Export current schematic to image.
img x y size xschem area to export
@ -902,7 +850,6 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
xschem print svg file.svg 400 300 [ -300 -200 300 200 ]
xschem print ps file.ps
xschem print pdf file.pdf</pre>
<li><kbd> print_hilight_net show</kbd></li><pre>
from highlighted nets/pins/labels:
show == 0 ==&gt; create pins from highlight nets
@ -911,19 +858,14 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
show == 3 ==&gt; show list of highlight net with path and label expansion in a dialog box
show == 4 ==&gt; create labels without i prefix from hilight nets
for show = 0, 2, 4 user should complete GUI placement of created objects </pre>
<li><kbd> print_spice_element inst</kbd></li><pre>
print spice raw netlist line for instance (number or name) 'inst' </pre>
<li><kbd> propagate_hilights [set clear] </kbd></li><pre>
Debug: wrapper to propagate_hilights() function </pre>
<li><kbd> push_undo</kbd></li><pre>
Push current state on undo stack </pre>
<li><kbd> raw_clear </kbd></li><pre>
Delete loaded simulation raw file </pre>
<li><kbd> raw_query loaded|value|index|values|datasets|vars|list </kbd></li><pre>
xschem raw_query list: get list of saved simulation variables
xschem raw_query vars: get number of simulation variables
@ -935,56 +877,42 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
xschem raw_query values node [dset] : print all simulation values of 'node' for dataset 'dset'
(default dset=0)
xschem raw_query points [dset] : print simulation points for dataset 'dset' (default dset=0)</pre>
<li><kbd> raw_read [file] [sim]</kbd></li><pre>
If a raw file is already loaded delete from memory
else load specified file and analysis 'sim' (dc, ac, tran, op, ...)
If 'sim' not specified load first section found in raw file. </pre>
<li><kbd> raw_read_from_attr [sim]</kbd></li><pre>
If a simulation raw file is already loaded delete from memory
else read section 'sim' (tran, dc, ac, op, ...) of base64 encoded data from a 'spice_data'
attribute of selected instance
If sim not given read first section found </pre>
<li><kbd> rebuild_connectivity </kbd></li><pre>
Rebuild logical connectivity abstraction of schematic </pre>
<li><kbd> rebuild_selection </kbd></li><pre>
Rebuild selection list</pre>
<li><kbd> rect [x1 y1 x2 y2] [pos]</kbd></li><pre>
if 'x1 y1 x2 y2'is given place recangle on current layer (rectcolor) at indicated coordinates.
if 'pos' is given insert at given position in rectangle array.
If no coordinates are given start a GUI operation of rectangle placement </pre>
<li><kbd> redo</kbd></li><pre>
Redo last undone action </pre>
<li><kbd> redraw</kbd></li><pre>
redraw window </pre>
<li><kbd> reload</kbd></li><pre>
Forced (be careful!) Reload current schematic from disk </pre>
<li><kbd> reload_symbols</kbd></li><pre>
Reload all used symbols from disk </pre>
<li><kbd> remove_symbols</kbd></li><pre>
Internal command: remove all symbol definitions </pre>
<li><kbd> replace_symbol inst new_symbol [fast]</kbd></li><pre>
Replace 'inst' symbol with 'new_symbol'
If doing multiple substitutions set 'fast' to 0 on first call and non zero on next calls
for faster operation
Example: xschem replace_symbol R3 capa.sym </pre>
<li><kbd> rotate</kbd></li><pre>
Rotate selected objects around their centers </pre>
<li><kbd> save</kbd></li><pre>
Save schematic if modified. Does not ask confirmation! </pre>
<li><kbd> saveas [file] [type]</kbd></li><pre>
save current schematic as 'file'
if file is empty ({}) use current schematic name
@ -994,12 +922,10 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
symbol: save as symbol (*.sym)
If not specified default to schematic (*.sch)
Does not ask confirmation if file name given</pre>
<li><kbd> schematic_in_new_window [new_process]</kbd></li><pre>
When a symbol is selected edit corresponding schematic in a new tab/window if not already open.
If nothing selected open another window of the second schematic (issues a warning).
if 'new_process' is given start a new xschem process </pre>
<li><kbd> search regex|exact select tok val</kbd></li><pre>
Search instances with attribute string containing 'tok' attribute and value 'val'
search can be exact ('exact') or as a regular expression ('regex')
@ -1013,38 +939,48 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
cell::name : will search for 'val' in the symbol name
cell::&lt;attr&gt; will search for 'val' in symbol attribute 'attr'
example: xschem search regex 0 cell::template GAIN=100</pre>
<li><kbd> select instance|wire|text id [clear]</kbd></li><pre>
Select indicated instance or wire or text.
For 'instance' 'id' can be the instance name or number
for 'wire' or 'text' 'id' is the position in the respective arrays
if 'clear' is specified does an unselect operation </pre>
<li><kbd> select_all</kbd></li><pre>
Selects all objects in schematic </pre>
<li><kbd> select_hilight_net</kbd></li><pre>
Select all highlight objects (wires, labels, pins, instances) </pre>
<li><kbd> selected_set</kbd></li><pre>
Return a list of selected instance names </pre>
<li><kbd> selected_wire</kbd></li><pre>
Return list of selected nets </pre>
<li><kbd> send_to_viewer</kbd></li><pre>
Send selected wires/net labels/pins/voltage source or ammeter currents to current
open viewer (gaw or bespice) </pre>
<li><kbd> set var value</kbd></li><pre>
Set C variable 'var' to 'value' </pre>
<ul>
<li><kbd> cadgrid </kbd> set cad grid (default: 20) </li>
<li><kbd> cadsnap </kbd> set mouse snap (default: 10) </li>
<li><kbd> color_ps </kbd> set color psoscript (1 or 0) </li>
<li><kbd> constrained_move </kbd> set constrained move (1=horiz, 2=vert, 0=none) </li>
<li><kbd> draw_window </kbd> set drawing to window (1 or 0) </li>
<li><kbd> format </kbd> set name of custom format attribute used for netlisting </li>
<li><kbd> header_text </kbd> set header metadata (used for license info) </li>
<li><kbd> hide_symbols </kbd> set to 0,1,2 for various hiding level of symbols </li>
<li><kbd> netlist_name </kbd> set custom netlist name </li>
<li><kbd> netlist_type </kbd> set netlisting mode (spice, verilog, vhdl, tedax, symbol) </li>
<li><kbd> no_draw </kbd> set no drawing flag (0 or 1) </li>
<li><kbd> no_undo </kbd> set to 1 to disable undo </li>
<li><kbd> rectcolor </kbd> set current layer (0, 1, .... , cadlayers-1) </li>
<li><kbd> sch_to_compare </kbd> st name of schematic to compare current window with </li>
<li><kbd> text_svg </kbd> set to 1 to use svg &lt;text&gt; elements </li>
<li><kbd> semaphore </kbd> debug </li>
<li><kbd> show_hidden_texts </kbd> set to 1 to enable showing texts with attr hide=true </li>
<li><kbd> sym_txt </kbd> set to 0 to hide symbol texts </li>
</ul>
<li><kbd> set_different_tok str new_str old_str</kbd></li><pre>
Return string 'str' replacing/adding/removing tokens that are different between 'new_str' and 'old_str' </pre>
<li><kbd> set_modify</kbd></li><pre>
Force modify status on current schematic </pre>
<li><kbd> setprop instance inst tok [val] [fast]</kbd></li><pre>
set attribute 'tok' of instance (name or number) 'inst' to value 'val'
If 'val' not given (no attribute value) delete attribute from instance
@ -1062,25 +998,18 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
If 'val' not given (no attribute value) delete attribute from text
If 'fast' argument is given does not redraw and is not undoable
If 'fastundo' s given same as above but action is undoable.</pre>
<li><kbd> simulate</kbd></li><pre>
Run a simulation (start simulator configured as default in Tools -&gt; Configure simulators and tools </pre>
<li><kbd> snap_wire </kbd></li><pre>
Start a GUI start snapped wire placement (click to start a wire to closest pin/net endpoint </pre>
<li><kbd> </kbd></li><pre>
subst_tok str tok newval
Start a GUI start snapped wire placement (click to start a wire to closest pin/net endpoint) </pre>
<li><kbd> subst_tok str tok newval</kbd></li><pre>
Return string 'str' with 'tok' attribute value replaced with 'newval' </pre>
<li><kbd> symbol_in_new_window [new_process]</kbd></li><pre>
When a symbol is selected edit it in a new tab/window if not already open.
If nothing selected open another window of the second schematic (issues a warning).
if 'new_process' is given start a new xschem process </pre>
<li><kbd> symbols</kbd></li><pre>
List all used symbols </pre>
<li><kbd> table_read [table_file]</kbd></li><pre>
If a simulation raw file is lodaded unload from memory.
else read a tabular file 'table_file'
@ -1104,75 +1033,54 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
0.0 0.0 1.8 0.3
0.1 0.0 1.5 0.6
... ... ... ...</pre>
<li><kbd> test </kbd></li><pre>
testmode </pre>
<li><kbd> toggle_colorscheme</kbd></li><pre>
Toggle dark/light colorscheme </pre>
<li><kbd> translate n str</kbd></li><pre>
Translate string 'str' replacing @xxx tokens with values in instance 'n' attributes </pre>
<li><kbd> trim_wires</kbd></li><pre>
Remove operlapping wires, join lines, trim wires at intersections </pre>
<li><kbd> undo</kbd></li><pre>
Undo last action </pre>
<li><kbd> undo_type disk|memory</kbd></li><pre>
Use disk file ('disk') or RAM ('memory') for undo bufer</pre>
<li><kbd> unhilight_all</kbd></li><pre>
Clear all highlights </pre>
<li><kbd> unhilight</kbd></li><pre>
Unhighlight selected nets/pins </pre>
<li><kbd> unselect_all</kbd></li><pre>
Unselect everything </pre>
<li><kbd> update_all_sym_bboxes</kbd></li><pre>
Update all symbol bounding boxes (useful if show_pin_net_names is set) </pre>
<li><kbd> view_prop</kbd></li><pre>
View attributes of selected element (read only)
if multiple selection show the first element (in xschem array order) </pre>
<li><kbd> warning_overlapped_symbols [sel]</kbd></li><pre>
Highlight or select (if 'sel' set to 1) perfectly overlapped instances
this is usually an error and difficult to grasp visually </pre>
<li><kbd> windowid</kbd></li><pre>
Used by xschem.tcl for configure events </pre>
<li><kbd> wire [x1 y1 x2 y2] [pos] [prop] [sel]</kbd></li><pre>
Place a new wire
if no coordinates are given start a GUI wire placement </pre>
<li><kbd> xcb_info</kbd></li><pre>
For debug </pre>
<li><kbd> zoom_box [x1 y1 x2 y2] [factor]</kbd></li><pre>
Zoom to specified coordinates, if 'factor' is given reduce view (factor &lt; 1.0)
or add border (factor &gt; 1.0)
If no coordinates are given start GUI zoom box operation </pre>
<li><kbd> zoom_full [center|nodraw|nolinewidth]</kbd></li><pre>
Set full view.
If 'center' is given center vire instead of lower-left align
If 'nodraw' is given don't redraw
If 'nolinewidth]' is given don't reset line widths. </pre>
<li><kbd> zoom_hilighted </kbd></li><pre>
Zoom to highlighted objects </pre>
<li><kbd> zoom_in</kbd></li><pre>
Zoom in drawing </pre>
<li><kbd> zoom_out</kbd></li><pre>
Zoom out drawing </pre>
<li><kbd> zoom_selected</kbd></li><pre>
Zoom to selection </pre>

View File

@ -58,218 +58,18 @@ static int get_instance(const char *s)
static void xschem_cmd_help(int argc, const char **argv)
{
char prog[PATH_MAX];
if( get_file_path("x-www-browser")[0] == '/' ) goto done;
if( get_file_path("firefox")[0] == '/' ) goto done;
if( get_file_path("chromium")[0] == '/' ) goto done;
if( get_file_path("chrome")[0] == '/' ) goto done;
if( get_file_path("xdg-open")[0] == '/' ) goto done;
done:
my_strncpy(prog, tclresult(), S(prog));
tclvareval("launcher {", "file://", XSCHEM_SHAREDIR,
"/../doc/xschem/xschem_man/developer_info.html#cmdref", "} ", prog, NULL);
Tcl_ResetResult(interp);
Tcl_AppendResult(interp,
"Xschem command language:\n",
" xschem subcommand [args]\n",
"\"xschem\" subcommands available:\n",
"align\n",
" Align selected part of schematic to current gid snap setting\n",
"annotate_op [filename]\n",
" Annotate schematic with operating point data. If filename not given get rootname from schemaic name\n",
"attach_labels\n",
" Attach labels to selected instance pins\n",
"bbox [begin | end]\n",
" bbox begin: start a bounding box drawing area setting\n",
" bbox end: end a bounding box drawing area setting, draw stuff and reset bbox\n",
"break_wires\n",
"build_colors\n",
"callback\n",
"case_insensitive\n",
"check_symbols\n",
"check_unique_names\n",
"circle\n",
"clear\n",
"clear_drawing\n",
"color_dim\n",
"compare_schematics\n",
"connected_nets\n",
"copy\n",
"copy_objects\n",
"count_items\n",
"create_plot_cmd\n",
"cut\n",
"debug\n",
"delete\n",
"delete_files\n",
"descend\n",
"descend_symbol\n",
"display_hilights\n",
"draw_graph\n",
"edit_file\n",
"edit_prop\n",
"edit_vi_prop\n",
"embed_rawfile\n",
"enable_layers\n",
"exit\n",
"expandlabel\n",
"find_nth\n",
"flip\n",
"fullscreen\n",
"get var\n",
" where \"var\" is one of:\n",
" schname [n]\n",
" get name of schematic, optionally of upper levels if(negative) n is provided\n",
" sch_path [n]\n",
" get pathname of schematic, optionally of upper levels if(negative) n is provided\n",
" backlayer\n",
" bbox_hilighted\n",
" bbox_selected\n",
" cadlayers\n",
" case_insensitive\n",
" color_ps\n",
" current_dirname\n",
" current_name\n",
" current_win_path\n",
" currsch\n",
" debug_var\n",
" draw_window\n",
" format\n",
" graph_lastsel\n",
" gridlayer\n",
" help\n",
" instances\n",
" lastsel\n",
" line_width\n",
" netlist_name\n",
" netlist_type\n",
" no_draw\n",
" ntabs\n",
" pinlayer\n",
" rectcolor\n",
" sellayer\n",
" semaphore\n",
" temp_dir\n",
" text_svg\n",
" textlayer\n",
" top_path\n",
" topwindow\n",
" version\n",
" wirelayer\n",
" xorigin\n",
" yorigin\n",
" zoom\n",
"getprop\n",
"get_tok\n",
"get_tok_size\n",
"globals\n",
"go_back\n",
"hash_file\n",
"help\n",
"hier_psprint\n",
"hilight\n",
"hilight_netname\n",
"instance\n",
"instance_bbox\n",
"instance_net\n",
"instance_nodemap\n",
"instance_pin_coord\n",
"instance_pins\n",
"instance_pos\n",
"instances_to_net\n",
"line\n",
"line_width\n",
"list_tokens\n",
"load\n",
"load_new_window\n",
"log\n",
"logic_set\n",
"make_sch\n",
"make_sch_from_sel\n",
"make_symbol\n",
"merge\n",
"move_objects\n",
"net_label\n",
"net_pin_mismatch\n",
"netlist\n",
"new_schematic\n",
"new_symbol_window\n",
"new_window\n",
"only_probes\n",
"origin\n",
"parselabel\n",
"paste\n",
"pinlist\n",
"place_symbol\n",
"place_text\n",
"polygon\n",
"preview_window\n",
"print\n",
"print_hilight_net\n",
"print_spice_element\n",
"propagate_hilights\n",
"push_undo\n",
"raw_clear\n",
"raw_query\n",
"raw_read\n",
"raw_read_from_attr\n",
"rebuild_connectivity\n",
"rect\n",
"redo\n",
"redraw\n",
"reload\n",
"reload_symbols\n",
"remove_symbols\n",
"replace_symbol\n",
"rotate\n",
"save\n",
"saveas\n",
"schematic_in_new_window\n",
"search\n",
"searchmenu\n",
"select\n",
"select_all\n",
"select_hilight_net\n",
"selected_set\n",
"selected_wire\n",
"send_to_viewer\n",
"set var value\n",
" where \"var\" is one of:\n",
" cadsnap\n",
" color_ps\n",
" constrained_move\n",
" draw_window\n",
" format\n",
" hide_symbols\n",
" netlist_name\n",
" netlist_type\n",
" no_draw\n",
" no_undo\n",
" rectcolor\n",
" text_svg\n",
" semaphore\n",
" show_hidden_texts\n",
" sym_txt\n",
"set_different_tok\n",
"set_modify\n",
"setprop\n",
"show_pin_net_names\n",
"simulate\n",
"snap_wire\n",
"subst_tok\n",
"symbol_in_new_window\n",
"symbols\n",
"test\n",
"toggle_colorscheme\n",
"translate\n",
"trim_wires\n",
"undo\n",
"undo_type\n",
"unhilight_all\n",
"unhilight\n",
"unselect_all\n",
"view_prop\n",
"warning_overlapped_symbols\n",
"windowid\n",
"windows\n",
"wire\n",
"zoom_box\n",
"zoom_full\n",
"zoom_hilighted\n",
"zoom_in\n",
"zoom_out\n",
"zoom_selected\n",
NULL);
}
/* can be used to reach C functions from the Tk shell. */
@ -941,17 +741,17 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(argc > 2) {
switch(argv[2][0]) {
case 'b':
if(!strcmp(argv[2], "backlayer")) {
if(!strcmp(argv[2], "backlayer")) { /* number of background layer */
Tcl_SetResult(interp, my_itoa(BACKLAYER), TCL_VOLATILE);
}
else if(!strcmp(argv[2], "bbox_hilighted")) {
else if(!strcmp(argv[2], "bbox_hilighted")) { /* bounding box of highlinhted objects */
xRect boundbox;
char res[2048];
calc_drawing_bbox(&boundbox, 2);
my_snprintf(res, S(res), "%g %g %g %g", boundbox.x1, boundbox.y1, boundbox.x2, boundbox.y2);
Tcl_SetResult(interp, res, TCL_VOLATILE);
}
else if(!strcmp(argv[2], "bbox_selected")) {
else if(!strcmp(argv[2], "bbox_selected")) { /* bounding box of selected objects */
xRect boundbox;
char res[2048];
calc_drawing_bbox(&boundbox, 1);
@ -960,57 +760,57 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
break;
case 'c':
if(!strcmp(argv[2], "cadlayers")) {
if(!strcmp(argv[2], "cadlayers")) { /* number of layers */
Tcl_SetResult(interp, my_itoa(cadlayers), TCL_VOLATILE);
}
else if(!strcmp(argv[2], "case_insensitive")) {
else if(!strcmp(argv[2], "case_insensitive")) { /* case_insensitive symbol matching */
Tcl_SetResult(interp, my_itoa(xctx->case_insensitive), TCL_VOLATILE);
}
else if(!strcmp(argv[2], "color_ps")) {
else if(!strcmp(argv[2], "color_ps")) { /* color postscript flag */
if(color_ps != 0 ) Tcl_SetResult(interp, "1",TCL_STATIC);
else Tcl_SetResult(interp, "0",TCL_STATIC);
}
else if(!strcmp(argv[2], "current_dirname")) {
else if(!strcmp(argv[2], "current_dirname")) { /* directory name of current design */
Tcl_SetResult(interp, xctx->current_dirname, TCL_VOLATILE);
}
else if(!strcmp(argv[2], "current_name")) {
else if(!strcmp(argv[2], "current_name")) { /* name of current design (no library path) */
Tcl_SetResult(interp, xctx->current_name, TCL_VOLATILE);
}
else if(!strcmp(argv[2], "current_win_path")) {
else if(!strcmp(argv[2], "current_win_path")) { /* path of current tab/window (.drw, .x1.drw, ...) */
Tcl_SetResult(interp, xctx->current_win_path, TCL_VOLATILE);
}
else if(!strcmp(argv[2], "currsch")) {
else if(!strcmp(argv[2], "currsch")) { /* hierarchy level of current schematic (start at 0) */
Tcl_SetResult(interp, my_itoa(xctx->currsch),TCL_VOLATILE);
}
break;
case 'd':
if(!strcmp(argv[2], "debug_var")) {
if(!strcmp(argv[2], "debug_var")) { /* debug level (0 = no debug, 1, 2, 3,...) */
Tcl_SetResult(interp, my_itoa(debug_var),TCL_VOLATILE);
}
else if(!strcmp(argv[2], "draw_window")) {
else if(!strcmp(argv[2], "draw_window")) { /* direct draw into window */
Tcl_SetResult(interp, my_itoa(xctx->draw_window),TCL_VOLATILE);
}
break;
case 'f':
if(!strcmp(argv[2], "format")) {
if(!strcmp(argv[2], "format")) { /* alternate format attribute to use in netlist (or NULL) */
if(!xctx->format ) Tcl_SetResult(interp, "<NULL>",TCL_STATIC);
else Tcl_SetResult(interp, xctx->format,TCL_VOLATILE);
}
break;
case 'g':
if(!strcmp(argv[2], "graph_lastsel")) {
if(!strcmp(argv[2], "graph_lastsel")) { /* number of last graph that was clicked */
Tcl_SetResult(interp, my_itoa(xctx->graph_lastsel),TCL_VOLATILE);
}
else if(!strcmp(argv[2], "gridlayer")) {
else if(!strcmp(argv[2], "gridlayer")) { /* layer number for grid */
Tcl_SetResult(interp, my_itoa(GRIDLAYER),TCL_VOLATILE);
}
break;
case 'h':
if(!strcmp(argv[2], "help")) {
if(!strcmp(argv[2], "help")) { /* command help */
if(help != 0 ) Tcl_SetResult(interp, "1",TCL_STATIC);
else Tcl_SetResult(interp, "0",TCL_STATIC);
}
else if(!strcmp(argv[2], "header_text")) {
else if(!strcmp(argv[2], "header_text")) { /* header metadata (license info etc) present in schematic */
if(xctx && xctx->header_text) {
Tcl_SetResult(interp, xctx->header_text, TCL_VOLATILE);
} else {
@ -1019,21 +819,21 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
break;
case 'i':
if(!strcmp(argv[2], "instances")) {
if(!strcmp(argv[2], "instances")) { /* number of instances in schematic */
Tcl_SetResult(interp, my_itoa(xctx->instances), TCL_VOLATILE);
}
break;
case 'l':
if(!strcmp(argv[2], "lastsel")) {
if(!strcmp(argv[2], "lastsel")) { /* number of selected objects */
rebuild_selected_array();
Tcl_SetResult(interp, my_itoa(xctx->lastsel),TCL_VOLATILE);
}
else if(!strcmp(argv[2], "line_width")) {
else if(!strcmp(argv[2], "line_width")) { /* get line width */
Tcl_SetResult(interp, dtoa(xctx->lw), TCL_VOLATILE);
}
break;
case 'n':
if(!strcmp(argv[2], "netlist_name")) {
if(!strcmp(argv[2], "netlist_name")) { /* netlist name if set. If 'fallback' given get default name */
if(argc > 3 && !strcmp(argv[3], "fallback")) {
char f[PATH_MAX];
if(xctx->netlist_type == CAD_SPICE_NETLIST) {
@ -1060,7 +860,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_SetResult(interp, xctx->netlist_name, TCL_VOLATILE);
}
}
else if(!strcmp(argv[2], "netlist_type")) {
else if(!strcmp(argv[2], "netlist_type")) { /* get current netlist type (spice/vhdl/verilog/tedax) */
if(xctx->netlist_type == CAD_SPICE_NETLIST) {
Tcl_SetResult(interp, "spice", TCL_STATIC);
}
@ -1080,34 +880,34 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_SetResult(interp, "unknown", TCL_STATIC);
}
}
else if(!strcmp(argv[2], "no_draw")) {
else if(!strcmp(argv[2], "no_draw")) { /* disable drawing */
if(xctx->no_draw != 0 )
Tcl_SetResult(interp, "1",TCL_STATIC);
else
Tcl_SetResult(interp, "0",TCL_STATIC);
}
else if(!strcmp(argv[2], "ntabs")) {
else if(!strcmp(argv[2], "ntabs")) { /* get number of additional tabs (0 = only one tab) */
Tcl_SetResult(interp, my_itoa(new_schematic("ntabs", NULL, NULL)),TCL_VOLATILE);
}
break;
case 'p':
if(!strcmp(argv[2], "pinlayer")) {
if(!strcmp(argv[2], "pinlayer")) { /* layer number for pins */
Tcl_SetResult(interp, my_itoa(PINLAYER),TCL_VOLATILE);
}
break;
case 'r':
if(!strcmp(argv[2], "rectcolor")) {
if(!strcmp(argv[2], "rectcolor")) { /* current layer number */
Tcl_SetResult(interp, my_itoa(xctx->rectcolor),TCL_VOLATILE);
}
break;
case 's':
if(!strcmp(argv[2], "sellayer")) {
if(!strcmp(argv[2], "sellayer")) { /* layer number for selection */
Tcl_SetResult(interp, my_itoa(SELLAYER),TCL_VOLATILE);
}
else if(!strcmp(argv[2], "semaphore")) {
else if(!strcmp(argv[2], "semaphore")) { /* used for debug */
Tcl_SetResult(interp, my_itoa(xctx->semaphore),TCL_VOLATILE);
}
else if(!strcmp(argv[2], "schname"))
else if(!strcmp(argv[2], "schname")) /* get full path of current sch. if 'n' given get sch of level 'n' */
{
int x;
/* allows to retrieve name of n-th parent schematic */
@ -1119,7 +919,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_SetResult(interp, xctx->sch[x], TCL_VOLATILE);
}
}
else if(!strcmp(argv[2], "sch_path"))
else if(!strcmp(argv[2], "sch_path")) /* get hierarchy path. if 'n' given get hierpath of level 'n' */
{
int x;
if(argc > 3) x = atoi(argv[3]);
@ -1130,14 +930,14 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_SetResult(interp, xctx->sch_path[x], TCL_VOLATILE);
}
}
else if(!strcmp(argv[2], "sch_to_compare"))
else if(!strcmp(argv[2], "sch_to_compare")) /* if set return schematic current design is compared with */
{
Tcl_SetResult(interp, xctx->sch_to_compare, TCL_VOLATILE);
}
break;
case 't':
#ifndef __unix__
if(!strcmp(argv[2], "temp_dir")) {
if(!strcmp(argv[2], "temp_dir")) { /* get windows temporary dir */
if(win_temp_dir[0] != '\0') Tcl_SetResult(interp, win_temp_dir, TCL_VOLATILE);
else {
TCHAR tmp_buffer_path[MAX_PATH];
@ -1169,53 +969,53 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
else
#endif
if(!strcmp(argv[2], "text_svg")) {
if(!strcmp(argv[2], "text_svg")) { /* return 1 if using <text> elements in svg export */
if(text_svg != 0 )
Tcl_SetResult(interp, "1",TCL_STATIC);
else
Tcl_SetResult(interp, "0",TCL_STATIC);
}
else if(!strcmp(argv[2], "textlayer")) {
else if(!strcmp(argv[2], "textlayer")) { /* layer number for texts */
Tcl_SetResult(interp, my_itoa(TEXTLAYER), TCL_VOLATILE);
}
/* top_path="" for main window, ".x1", ".x2", ... for additional windows.
* always "" in tabbed interface */
else if(!strcmp(argv[2], "top_path")) {
else if(!strcmp(argv[2], "top_path")) { /* get top hier path of current window (always "") for tabbed if */
Tcl_SetResult(interp, xctx->top_path, TCL_VOLATILE);
}
/* same as above but main window returned as "." */
else if(!strcmp(argv[2], "topwindow")) {
else if(!strcmp(argv[2], "topwindow")) { /* same as top_path but main window returned as "." */
char *top_path;
top_path = xctx->top_path[0] ? xctx->top_path : ".";
Tcl_SetResult(interp, top_path,TCL_VOLATILE);
}
break;
case 'v':
if(!strcmp(argv[2], "version")) {
if(!strcmp(argv[2], "version")) { /* return xschem version */
Tcl_SetResult(interp, XSCHEM_VERSION, TCL_VOLATILE);
}
break;
case 'w':
if(!strcmp(argv[2], "wirelayer")) {
if(!strcmp(argv[2], "wirelayer")) { /* layer used for wires */
Tcl_SetResult(interp, my_itoa(WIRELAYER), TCL_VOLATILE);
}
break;
case 'x':
if(!strcmp(argv[2], "xorigin")) {
if(!strcmp(argv[2], "xorigin")) { /* x coordinate of origin */
char s[128];
my_snprintf(s, S(s), "%.16g", xctx->xorigin);
Tcl_SetResult(interp, s,TCL_VOLATILE);
}
break;
case 'y':
if(!strcmp(argv[2], "yorigin")) {
if(!strcmp(argv[2], "yorigin")) { /* y coordinate of origin */
char s[128];
my_snprintf(s, S(s), "%.16g", xctx->yorigin);
Tcl_SetResult(interp, s,TCL_VOLATILE);
}
break;
case 'z':
if(!strcmp(argv[2], "zoom")) {
if(!strcmp(argv[2], "zoom")) { /* zoom level */
char s[128];
my_snprintf(s, S(s), "%.16g", xctx->zoom);
Tcl_SetResult(interp, s,TCL_VOLATILE);
@ -3050,38 +2850,38 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
{
if(argc > 3) {
if(argv[2][0] < 'n') {
if(!strcmp(argv[2], "cadgrid")) {
if(!strcmp(argv[2], "cadgrid")) { /* set cad grid (default: 20) */
set_grid( atof(argv[3]) );
}
else if(!strcmp(argv[2], "cadsnap")) {
else if(!strcmp(argv[2], "cadsnap")) { /* set mouse snap (default: 10) */
set_snap( atof(argv[3]) );
}
else if(!strcmp(argv[2], "color_ps")) {
else if(!strcmp(argv[2], "color_ps")) { /* set color psoscript (1 or 0) */
color_ps=atoi(argv[3]);
}
else if(!strcmp(argv[2], "constrained_move")) {
else if(!strcmp(argv[2], "constrained_move")) { /* set constrained move (1=horiz, 2=vert, 0=none) */
constrained_move = atoi(argv[3]);
}
else if(!strcmp(argv[2], "draw_window")) {
else if(!strcmp(argv[2], "draw_window")) { /* set drawing to window (1 or 0) */
xctx->draw_window=atoi(argv[3]);
}
else if(!strcmp(argv[2], "format")) {
else if(!strcmp(argv[2], "format")) { /* set name of custom format attribute used for netlisting */
my_strdup(_ALLOC_ID_, &xctx->format, argv[3]);
}
else if(!strcmp(argv[2], "header_text")) {
else if(!strcmp(argv[2], "header_text")) { /* set header metadata (used for license info) */
if(!xctx->header_text || strcmp(xctx->header_text, argv[3])) {
set_modify(1); xctx->push_undo();
my_strdup2(_ALLOC_ID_, &xctx->header_text, argv[3]);
}
}
else if(!strcmp(argv[2], "hide_symbols")) {
else if(!strcmp(argv[2], "hide_symbols")) { /* set to 0,1,2 for various hiding level of symbols */
xctx->hide_symbols=atoi(argv[3]);
}
} else { /* argv[2][0] >= 'n' */
if(!strcmp(argv[2], "netlist_name")) {
if(!strcmp(argv[2], "netlist_name")) { /* set custom netlist name */
my_strncpy(xctx->netlist_name, argv[3], S(xctx->netlist_name));
}
else if(!strcmp(argv[2], "netlist_type"))
else if(!strcmp(argv[2], "netlist_type")) /* set netlisting mode (spice, verilog, vhdl, tedax, symbol) */
{
if(!strcmp(argv[3], "spice")){
xctx->netlist_type=CAD_SPICE_NETLIST;
@ -3103,15 +2903,15 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
set_tcl_netlist_type();
}
else if(!strcmp(argv[2], "no_draw")) {
else if(!strcmp(argv[2], "no_draw")) { /* set no drawing flag (0 or 1) */
int s = atoi(argv[3]);
xctx->no_draw=s;
}
else if(!strcmp(argv[2], "no_undo")) {
else if(!strcmp(argv[2], "no_undo")) { /* set to 1 to disable undo */
int s = atoi(argv[3]);
xctx->no_undo=s;
}
else if(!strcmp(argv[2], "rectcolor")) {
else if(!strcmp(argv[2], "rectcolor")) { /* set current layer (0, 1, .... , cadlayers-1) */
xctx->rectcolor=atoi(argv[3]);
if(xctx->rectcolor < 0 ) xctx->rectcolor = 0;
if(xctx->rectcolor >= cadlayers ) xctx->rectcolor = cadlayers - 1;
@ -3120,21 +2920,21 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
change_layer();
}
}
else if(!strcmp(argv[2], "sch_to_compare")) {
else if(!strcmp(argv[2], "sch_to_compare")) { /* st name of schematic to compare current window with */
my_strncpy(xctx->sch_to_compare, abs_sym_path(argv[3], ""), S(xctx->sch_to_compare));
}
else if(!strcmp(argv[2], "text_svg")) {
else if(!strcmp(argv[2], "text_svg")) { /* set to 1 to use svg <text> elements */
text_svg=atoi(argv[3]);
}
else if(!strcmp(argv[2], "semaphore")) {
else if(!strcmp(argv[2], "semaphore")) { /* debug */
dbg(1, "scheduler(): set semaphore to %s\n", argv[3]);
xctx->semaphore=atoi(argv[3]);
}
else if(!strcmp(argv[2], "show_hidden_texts")) {
else if(!strcmp(argv[2], "show_hidden_texts")) { /* set to 1 to enable showing texts with attr hide=true */
dbg(1, "scheduler(): set show_hidden_texts to %s\n", argv[3]);
xctx->show_hidden_texts=atoi(argv[3]);
}
else if(!strcmp(argv[2], "sym_txt")) {
else if(!strcmp(argv[2], "sym_txt")) { /* set to 0 to hide symbol texts */
xctx->sym_txt=atoi(argv[3]);
}
else {
@ -3397,7 +3197,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
}
/* simulate
* Run a simulation (start simulator configured as default in Tools -> Configure simulators and tools */
* Run a simulation (start simulator configured as default in Tools -> Configure simulators and tools) */
else if(!strcmp(argv[1], "simulate") )
{
if(set_netlist_dir(0, NULL) ) {
@ -3406,16 +3206,15 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
/* snap_wire
* Start a GUI start snapped wire placement (click to start a wire to closest pin/net endpoint */
* Start a GUI start snapped wire placement (click to start a wire to closest pin/net endpoint) */
else if(!strcmp(argv[1], "snap_wire"))
{
xctx->ui_state |= MENUSTARTSNAPWIRE;
}
/*
* subst_tok str tok newval
/* subst_tok str tok newval
* Return string 'str' with 'tok' attribute value replaced with 'newval' */
else if(!strcmp(argv[1], "subst_tok") )
else if(!strcmp(argv[1], "subst_tok"))
{
char *s=NULL;
if(argc < 5) {Tcl_SetResult(interp, "Missing arguments", TCL_STATIC);return TCL_ERROR;}

View File

@ -986,7 +986,7 @@ typedef struct {
char *format; /* "format", "verilog_format", "vhdl_format" or "tedax_format" */
char *top_path;
/* top_path is the path prefix of drawing canvas (current_win_path):
*
* top_path is always "" in tabbed interface
* current_win_path
* canvas top_path
* ----------------------------

View File

@ -5314,7 +5314,7 @@ set tctx::global_list {
graph_selected graph_sort graph_unlocked hide_empty_graphs hide_symbols hsize
incr_hilight infowindow_text input_line_cmd input_line_data launcher_default_program
light_colors line_width live_cursor2_backannotate local_netlist_dir
lvs_netlist measure_text netlist_show
lvs_netlist measure_text netlist_dir netlist_show
netlist_type no_change_attrs nolist_libs noprint_libs old_selected_tok only_probes path pathlist
persistent_command preserve_unchanged_attrs prev_symbol ps_colors rainbow_colors
rawfile_loaded rcode recentfile