The following are xschem specific tcl commands.
All commands are prefixed by the xschem keyword.
@@ -476,164 +476,162 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
Resets UI state, unselect all and abort any pending operation
-
Start a GUI placement of a symbol pin
-
Start a GUI placement of a graph object
-
Ask user to choose a png file and start a GUI placement of the image
-
Align currently selected objects to current snap setting
-
Annotate operating point data into current schematic.
use <schematic name>.raw or use supplied argument as raw file to open
look for operating point data and annotate voltages/currents into schematic
-
Start a GUI placement of an arc.
User should click 3 unaligned points to define the arc
-
Attach net labels to selected component(s) instance(s)
-
Start/end bounding box calculation: parameter is either 'begin' or 'end'
-
Break wires at selected instance pins
-
Rebuild color palette using values of tcl vars dim_value and dim_bg
-
Invoke the callback event dispatcher with a software event
-
Set case insensitive symbol lookup. Use only on case insensitive filesystems
-
List all used symbols in current schematic and warn if some symbol is newer
-
Check if all instances have a unique refdes (name attribute in xschem),
highlight such instances. If second parameter is '1' rename duplicates
-
Start a GUI placement of a circle.
User should click 3 unaligned points to define the circle
-
Clear current schematic window. Resets hierarchy level. Remove symbols
the 'force' parameter will not ask to save existing modified schematic.
the 'schematic' or 'symbol' parameter specifies to default to a schematic
or symbol window (default: schematic)
-
Clears drawing but does not purge symbols
-
Dim colors or brite colors depending on value parameter: -5 <= value <= 5
-
Compare currently loaded schematic with another 'sch_file' schematic.
if no file is given prompt user to choose one
-
Selected nets connected to currently selected net or net label/pin.
if '1' argument is given, stop at wire junctions
-
Copy selection to clipboard
-
Start a GUI copy operation
-
Debug command
-
Create an xplot file in netlist/simulation directory with the list of highlighted nodes
in a format the selected waveform viewer understands (bespice, gaw, ngspice)
-
Cut selection to clipboard
-
Set xschem in debug mode.'n' is the debug level (0=no debug). Higher levels yield more debug info.
-
Delete selection
-
Bring up a file selector the user can use to delete files
-
Descend into selected component instance. Optional number 'n' specifies the
instance number to descend into for vector instances (default: 0).
-
Descend into the symbol view of selected component instance
-
Print a list of highlighted objects (nets, net labels/pins, instances)
-
Redraw graph rectangle number 'n'. If the optional 'flags' integer is given it will be used as the
flags bitmask to use while drawing (can be used to restrict what to redraw)
-
Edit xschem file of current schematic if nothing is selected.
Edit .sym file if a component is selected.
-
Edit global schematic/symbol attributes or attributes of currently selected instances
-
Edit global schematic/symbol attributes or attributes of currently selected instances
using a text editor (defined in tcl 'editor' variable)
-
Embed base 64 encoded 'raw_file' into currently selected element as a 'spice_data'
attribute.
-
Enable/disable layers depending on tcl array variable enable_layer()
-
Exit the program, ask for confirm if current file modified.
-
Expand vectored labels/instance names:
xschem expandlabel {2*A[3:0]} --> A[3],A[2],A[1],A[0],A[3],A[2],A[1],A[0] 8
last field is the number of bits
since [ and ] are TCL special characters argument must be quoted with { and }
-
Find n-th field string separated by characters in sep. 1st field is in position 1
xschem find_nth {aaa,bbb,ccc,ddd} {,} 2 --> bbb
-
Flip selection horizontally
-
Flip selection horizontally, each object around its center
-
Toggle fullscreen modes: fullscreen with menu & status, fullscreen, normal
-
Get C variable/constant 'var'
-
+
Get the full attribute string of 'inst'
@@ -669,92 +667,70 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
('inst' can be an instance name or instance number)
('pin' can be a pin name or pin number)
-
get value of token 'tok' in string 'str'
'with_quotes' (default:0) is an integer passed to get_tok_value()
-
Get length of last looked up attribute name (not its value)
if returned value is 0 it means that last searched attribute did not exist
-
Return various global variables used in the program
-
Go up one level (pop) in hierarchy
-
Do a simple hash of 'file'
'skip_path_lines' is an integer (default: 0) passed to hash_file()
-
Do a simple hashing of string 'str'
-
Print command help
-
Hierarchical postscript / pdf print
if 'file' is not given show a fileselector dialog box
-
Highlight selected element/pins/labels/nets
if 'drill' is given propagate net highlights through conducting elements
(elements that have the 'propag' attribute on pins )
-
Highlight instance 'inst'
'inst' can be an instance name or number
-
Highlight net name 'net'
-
Place a new instance of symbol 'sym_name' at position x,y,
rotation and flip set to 'rot', 'flip'
if 'prop' is given it is the new instance attribute string (default: symbol template string)
if 'first_call' is given it must be 1 on first call and zero on following calls
It is used only for efficiency reasons if placing multiple instances
-
return instance and symbol bounding boxes
'inst' can be an instance name or number
-
Return the name of the net attached to pin 'pin' of instance 'inst'
Example: xschem instance_net x3 MINUS --> REF
-
Return the instance name followed by a list of 'pin net' associations
example: xschem instance_nodemap x3
--> x3 PLUS LED OUT LEVEL MINUS REF
instance x3 pin PLUS is attached to net LED, pin OUT to net LEVEL and so on...
-
Return the name and coordinates of pin with attribute 'attr' set to 'value' of instance 'inst'
'inst can be an instance name or a number
Example: xschem instance_pin_coord x3 name MINUS --> {MINUS} 600 -840
-
Return list of pins of instance 'inst'
'inst can be an instance name or a number
-
Get number (position) of instance name 'inst'
-
Return list of instances names and pins attached to net 'net'
Example: xschem instances_to_net PANEL
--> { {Vsw} {plus} {580} {-560} } { {p2} {p} {660} {-440} } { {Vpanel1} {minus} {600} {-440} }
-
Place a line on current layer (rectcolor)
if integer number 'pos' is given place lien at indicated position in the line array.
-
set line width to floating point number 'n'
-
List all schematics at or below current hierarchy with modification times.
Example: xschem list_hiearchy
@@ -763,31 +739,25 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
20230211_010031 {/home/schippes/xschem-repo/trunk/xschem_library/ngspice/pv_ngspice.sch}
20221011_175308 {/home/schippes/xschem-repo/trunk/xschem_library/ngspice/diode_ngspice.sch}
20221014_091945 {/home/schippes/xschem-repo/trunk/xschem_library/ngspice/comp_ngspice.sch}
-
Sorted list of highlight nets, separated by character 'sep' (default: space)
-
List tokens in string 'str'
with_quotes:
0: eat non escaped quotes (")
1: return unescaped quotes as part of the token value if they are present
2: eat backslashes
-
Load a new file 'f'.
'force': do not ask to save modified file or warn if opening an already open file
'noundoreset': do not reset the undo history
'symbol': do not load symbols (used if loading a symbol instead of a schematic)
'nofullzoom': do not do a fll zoom on new schematic.
-
Load schematic in a new tab/window. If 'f' not given prompt user
-
if 'f' is given output stderr messages to file 'f'
if 'f' is not given and a file log is open, close log file and resume logging to stderr
-
Set selected nets, net labels or pins to logic level 'n' 'num' times.
'n':
@@ -797,7 +767,6 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
3 set to logic value Z
-1 toggle logic valie (1->0, 0->1)
the 'num' parameter is essentially useful only with 'toggle' (-1) value
-
Set selected nets, net labels or pins to logic level 'n' 'num' times.
'n':
@@ -807,35 +776,27 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
3 set to logic value Z
-1 toggle logic valie (1->0, 0->1)
the 'num' parameter is essentially useful only with 'toggle' (-1) value
-
create an LCC instance from selection and place it instead of selection
also ask if a symbol (.sym) file needs to be created
-
From current schematic (circuit.sch) create a symbol (circuit.sym)
using ipin.sym, opin.sym, iopin.sym in schematic
to deduce symbol interface pins.
-
Merge another file. if 'f' not given prompt user.
-
Start a move operation on selection and let user terminate the operation in the GUI
if dx and dy are given move by that amount.
-
Place a new net label
'type': 1: place a 'lab_pin.sym' label
0: place a 'lab_wire.sym' label
User should complete the placement in the GUI.
-
Highlight nets attached to selected symbols with a different name than symbol pin
-
do a netlist of current schematic in currently defined netlist format
-
Open/destroy a new tab or window
create: create new empty window or with 'file' loaded if 'file' given.
@@ -847,53 +808,40 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
switch_tab: switch context to specified 'winpath' tab
Main window/tab has winpath set to .drw,
Additional windows/tabs have winpath set to .x1.drw, .x2.drw and so on...
-
Start a new xschem process for a symbol.
If 'f' is given load specified symbol.
-
Start a new xschem process for a schematic.
If 'f' is given load specified schematic.
-
dim schematic to better show highlights
-
Move origin to 'x, y', optionally changing zoom level to 'zoom'
-
debug command to test parse_cmd_string()
splits a command string into argv-like arguments
return # of args in *argc
argv[*argc] is always set to NULL
-
Debug command to test vector net syntax parser
-
Paste clipboard. If 'x y' not given user should complete placement in the GUI
-
List all pins of instance 'inst'
Example: xschem pinlist x3
-->
{ {0} {name=PLUS dir=in } } { {1} {name=OUT dir=out } } { {2} {name=MINUS dir=in } }
-
Start a GUI placement operation of specified 'sym_name' symbol.
If 'sym_name' not given prompt user
'prop' is the attribute string of the symbol. If not given take from symbol template attribute.
-
Start a GUI placement of a text object
-
Start a GUI placement of a polygon
-
used in fileselector to show a schematic preview.
-
Export current schematic to image.
img x y size xschem area to export
@@ -902,7 +850,6 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
xschem print svg file.svg 400 300 [ -300 -200 300 200 ]
xschem print ps file.ps
xschem print pdf file.pdf
-
from highlighted nets/pins/labels:
show == 0 ==> create pins from highlight nets
@@ -911,19 +858,14 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
show == 3 ==> show list of highlight net with path and label expansion in a dialog box
show == 4 ==> create labels without i prefix from hilight nets
for show = 0, 2, 4 user should complete GUI placement of created objects
-
print spice raw netlist line for instance (number or name) 'inst'
-
Debug: wrapper to propagate_hilights() function
-
Push current state on undo stack
-
Delete loaded simulation raw file
-
xschem raw_query list: get list of saved simulation variables
xschem raw_query vars: get number of simulation variables
@@ -935,56 +877,42 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
xschem raw_query values node [dset] : print all simulation values of 'node' for dataset 'dset'
(default dset=0)
xschem raw_query points [dset] : print simulation points for dataset 'dset' (default dset=0)
-
If a raw file is already loaded delete from memory
else load specified file and analysis 'sim' (dc, ac, tran, op, ...)
If 'sim' not specified load first section found in raw file.
-
If a simulation raw file is already loaded delete from memory
else read section 'sim' (tran, dc, ac, op, ...) of base64 encoded data from a 'spice_data'
attribute of selected instance
If sim not given read first section found
-
Rebuild logical connectivity abstraction of schematic
-
Rebuild selection list
-
if 'x1 y1 x2 y2'is given place recangle on current layer (rectcolor) at indicated coordinates.
if 'pos' is given insert at given position in rectangle array.
If no coordinates are given start a GUI operation of rectangle placement
-
Redo last undone action
-
redraw window
-
Forced (be careful!) Reload current schematic from disk
-
Reload all used symbols from disk
-
Internal command: remove all symbol definitions
-
Replace 'inst' symbol with 'new_symbol'
If doing multiple substitutions set 'fast' to 0 on first call and non zero on next calls
for faster operation
Example: xschem replace_symbol R3 capa.sym
-
Rotate selected objects around their centers
-
Save schematic if modified. Does not ask confirmation!
-
save current schematic as 'file'
if file is empty ({}) use current schematic name
@@ -994,12 +922,10 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
symbol: save as symbol (*.sym)
If not specified default to schematic (*.sch)
Does not ask confirmation if file name given
-
When a symbol is selected edit corresponding schematic in a new tab/window if not already open.
If nothing selected open another window of the second schematic (issues a warning).
if 'new_process' is given start a new xschem process
-
Search instances with attribute string containing 'tok' attribute and value 'val'
search can be exact ('exact') or as a regular expression ('regex')
@@ -1013,38 +939,48 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
cell::name : will search for 'val' in the symbol name
cell::<attr> will search for 'val' in symbol attribute 'attr'
example: xschem search regex 0 cell::template GAIN=100
-
Select indicated instance or wire or text.
For 'instance' 'id' can be the instance name or number
for 'wire' or 'text' 'id' is the position in the respective arrays
if 'clear' is specified does an unselect operation
-
Selects all objects in schematic
-
Select all highlight objects (wires, labels, pins, instances)
-
Return a list of selected instance names
-
Return list of selected nets
-
Send selected wires/net labels/pins/voltage source or ammeter currents to current
open viewer (gaw or bespice)
-
Set C variable 'var' to 'value'
-
+
Return string 'str' replacing/adding/removing tokens that are different between 'new_str' and 'old_str'
-
Force modify status on current schematic
-
set attribute 'tok' of instance (name or number) 'inst' to value 'val'
If 'val' not given (no attribute value) delete attribute from instance
@@ -1062,25 +998,18 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
If 'val' not given (no attribute value) delete attribute from text
If 'fast' argument is given does not redraw and is not undoable
If 'fastundo' s given same as above but action is undoable.
-
Run a simulation (start simulator configured as default in Tools -> Configure simulators and tools
-
- Start a GUI start snapped wire placement (click to start a wire to closest pin/net endpoint- -
- subst_tok str tok newval + Start a GUI start snapped wire placement (click to start a wire to closest pin/net endpoint)+
Return string 'str' with 'tok' attribute value replaced with 'newval'
-
When a symbol is selected edit it in a new tab/window if not already open.
If nothing selected open another window of the second schematic (issues a warning).
if 'new_process' is given start a new xschem process
-
List all used symbols
-
If a simulation raw file is lodaded unload from memory.
else read a tabular file 'table_file'
@@ -1104,75 +1033,54 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
0.0 0.0 1.8 0.3
0.1 0.0 1.5 0.6
... ... ... ...
-
testmode
-
Toggle dark/light colorscheme
-
Translate string 'str' replacing @xxx tokens with values in instance 'n' attributes
-
Remove operlapping wires, join lines, trim wires at intersections
-
Undo last action
-
Use disk file ('disk') or RAM ('memory') for undo bufer
-
Clear all highlights
-
Unhighlight selected nets/pins
-
Unselect everything
-
Update all symbol bounding boxes (useful if show_pin_net_names is set)
-
View attributes of selected element (read only)
if multiple selection show the first element (in xschem array order)
-
Highlight or select (if 'sel' set to 1) perfectly overlapped instances
this is usually an error and difficult to grasp visually
-
Used by xschem.tcl for configure events
-
Place a new wire
if no coordinates are given start a GUI wire placement
-
For debug
-
Zoom to specified coordinates, if 'factor' is given reduce view (factor < 1.0)
or add border (factor > 1.0)
If no coordinates are given start GUI zoom box operation
-
Set full view.
If 'center' is given center vire instead of lower-left align
If 'nodraw' is given don't redraw
If 'nolinewidth]' is given don't reset line widths.
-
Zoom to highlighted objects
-
Zoom in drawing
-
Zoom out drawing
-
Zoom to selection
diff --git a/src/scheduler.c b/src/scheduler.c
index e4fdbd73..8368af67 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -58,218 +58,18 @@ static int get_instance(const char *s)
static void xschem_cmd_help(int argc, const char **argv)
{
+
+ char prog[PATH_MAX];
+ if( get_file_path("x-www-browser")[0] == '/' ) goto done;
+ if( get_file_path("firefox")[0] == '/' ) goto done;
+ if( get_file_path("chromium")[0] == '/' ) goto done;
+ if( get_file_path("chrome")[0] == '/' ) goto done;
+ if( get_file_path("xdg-open")[0] == '/' ) goto done;
+ done:
+ my_strncpy(prog, tclresult(), S(prog));
+ tclvareval("launcher {", "file://", XSCHEM_SHAREDIR,
+ "/../doc/xschem/xschem_man/developer_info.html#cmdref", "} ", prog, NULL);
Tcl_ResetResult(interp);
- Tcl_AppendResult(interp,
- "Xschem command language:\n",
- " xschem subcommand [args]\n",
- "\"xschem\" subcommands available:\n",
- "align\n",
- " Align selected part of schematic to current gid snap setting\n",
- "annotate_op [filename]\n",
- " Annotate schematic with operating point data. If filename not given get rootname from schemaic name\n",
- "attach_labels\n",
- " Attach labels to selected instance pins\n",
- "bbox [begin | end]\n",
- " bbox begin: start a bounding box drawing area setting\n",
- " bbox end: end a bounding box drawing area setting, draw stuff and reset bbox\n",
- "break_wires\n",
- "build_colors\n",
- "callback\n",
- "case_insensitive\n",
- "check_symbols\n",
- "check_unique_names\n",
- "circle\n",
- "clear\n",
- "clear_drawing\n",
- "color_dim\n",
- "compare_schematics\n",
- "connected_nets\n",
- "copy\n",
- "copy_objects\n",
- "count_items\n",
- "create_plot_cmd\n",
- "cut\n",
- "debug\n",
- "delete\n",
- "delete_files\n",
- "descend\n",
- "descend_symbol\n",
- "display_hilights\n",
- "draw_graph\n",
- "edit_file\n",
- "edit_prop\n",
- "edit_vi_prop\n",
- "embed_rawfile\n",
- "enable_layers\n",
- "exit\n",
- "expandlabel\n",
- "find_nth\n",
- "flip\n",
- "fullscreen\n",
- "get var\n",
- " where \"var\" is one of:\n",
- " schname [n]\n",
- " get name of schematic, optionally of upper levels if(negative) n is provided\n",
- " sch_path [n]\n",
- " get pathname of schematic, optionally of upper levels if(negative) n is provided\n",
- " backlayer\n",
- " bbox_hilighted\n",
- " bbox_selected\n",
- " cadlayers\n",
- " case_insensitive\n",
- " color_ps\n",
- " current_dirname\n",
- " current_name\n",
- " current_win_path\n",
- " currsch\n",
- " debug_var\n",
- " draw_window\n",
- " format\n",
- " graph_lastsel\n",
- " gridlayer\n",
- " help\n",
- " instances\n",
- " lastsel\n",
- " line_width\n",
- " netlist_name\n",
- " netlist_type\n",
- " no_draw\n",
- " ntabs\n",
- " pinlayer\n",
- " rectcolor\n",
- " sellayer\n",
- " semaphore\n",
- " temp_dir\n",
- " text_svg\n",
- " textlayer\n",
- " top_path\n",
- " topwindow\n",
- " version\n",
- " wirelayer\n",
- " xorigin\n",
- " yorigin\n",
- " zoom\n",
- "getprop\n",
- "get_tok\n",
- "get_tok_size\n",
- "globals\n",
- "go_back\n",
- "hash_file\n",
- "help\n",
- "hier_psprint\n",
- "hilight\n",
- "hilight_netname\n",
- "instance\n",
- "instance_bbox\n",
- "instance_net\n",
- "instance_nodemap\n",
- "instance_pin_coord\n",
- "instance_pins\n",
- "instance_pos\n",
- "instances_to_net\n",
- "line\n",
- "line_width\n",
- "list_tokens\n",
- "load\n",
- "load_new_window\n",
- "log\n",
- "logic_set\n",
- "make_sch\n",
- "make_sch_from_sel\n",
- "make_symbol\n",
- "merge\n",
- "move_objects\n",
- "net_label\n",
- "net_pin_mismatch\n",
- "netlist\n",
- "new_schematic\n",
- "new_symbol_window\n",
- "new_window\n",
- "only_probes\n",
- "origin\n",
- "parselabel\n",
- "paste\n",
- "pinlist\n",
- "place_symbol\n",
- "place_text\n",
- "polygon\n",
- "preview_window\n",
- "print\n",
- "print_hilight_net\n",
- "print_spice_element\n",
- "propagate_hilights\n",
- "push_undo\n",
- "raw_clear\n",
- "raw_query\n",
- "raw_read\n",
- "raw_read_from_attr\n",
- "rebuild_connectivity\n",
- "rect\n",
- "redo\n",
- "redraw\n",
- "reload\n",
- "reload_symbols\n",
- "remove_symbols\n",
- "replace_symbol\n",
- "rotate\n",
- "save\n",
- "saveas\n",
- "schematic_in_new_window\n",
- "search\n",
- "searchmenu\n",
- "select\n",
- "select_all\n",
- "select_hilight_net\n",
- "selected_set\n",
- "selected_wire\n",
- "send_to_viewer\n",
- "set var value\n",
- " where \"var\" is one of:\n",
- " cadsnap\n",
- " color_ps\n",
- " constrained_move\n",
- " draw_window\n",
- " format\n",
- " hide_symbols\n",
- " netlist_name\n",
- " netlist_type\n",
- " no_draw\n",
- " no_undo\n",
- " rectcolor\n",
- " text_svg\n",
- " semaphore\n",
- " show_hidden_texts\n",
- " sym_txt\n",
- "set_different_tok\n",
- "set_modify\n",
- "setprop\n",
- "show_pin_net_names\n",
- "simulate\n",
- "snap_wire\n",
- "subst_tok\n",
- "symbol_in_new_window\n",
- "symbols\n",
- "test\n",
- "toggle_colorscheme\n",
- "translate\n",
- "trim_wires\n",
- "undo\n",
- "undo_type\n",
- "unhilight_all\n",
- "unhilight\n",
- "unselect_all\n",
- "view_prop\n",
- "warning_overlapped_symbols\n",
- "windowid\n",
- "windows\n",
- "wire\n",
- "zoom_box\n",
- "zoom_full\n",
- "zoom_hilighted\n",
- "zoom_in\n",
- "zoom_out\n",
- "zoom_selected\n",
- NULL);
}
/* can be used to reach C functions from the Tk shell. */
@@ -941,17 +741,17 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(argc > 2) {
switch(argv[2][0]) {
case 'b':
- if(!strcmp(argv[2], "backlayer")) {
+ if(!strcmp(argv[2], "backlayer")) { /* number of background layer */
Tcl_SetResult(interp, my_itoa(BACKLAYER), TCL_VOLATILE);
}
- else if(!strcmp(argv[2], "bbox_hilighted")) {
+ else if(!strcmp(argv[2], "bbox_hilighted")) { /* bounding box of highlinhted objects */
xRect boundbox;
char res[2048];
calc_drawing_bbox(&boundbox, 2);
my_snprintf(res, S(res), "%g %g %g %g", boundbox.x1, boundbox.y1, boundbox.x2, boundbox.y2);
Tcl_SetResult(interp, res, TCL_VOLATILE);
}
- else if(!strcmp(argv[2], "bbox_selected")) {
+ else if(!strcmp(argv[2], "bbox_selected")) { /* bounding box of selected objects */
xRect boundbox;
char res[2048];
calc_drawing_bbox(&boundbox, 1);
@@ -960,57 +760,57 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
break;
case 'c':
- if(!strcmp(argv[2], "cadlayers")) {
+ if(!strcmp(argv[2], "cadlayers")) { /* number of layers */
Tcl_SetResult(interp, my_itoa(cadlayers), TCL_VOLATILE);
}
- else if(!strcmp(argv[2], "case_insensitive")) {
+ else if(!strcmp(argv[2], "case_insensitive")) { /* case_insensitive symbol matching */
Tcl_SetResult(interp, my_itoa(xctx->case_insensitive), TCL_VOLATILE);
}
- else if(!strcmp(argv[2], "color_ps")) {
+ else if(!strcmp(argv[2], "color_ps")) { /* color postscript flag */
if(color_ps != 0 ) Tcl_SetResult(interp, "1",TCL_STATIC);
else Tcl_SetResult(interp, "0",TCL_STATIC);
}
- else if(!strcmp(argv[2], "current_dirname")) {
+ else if(!strcmp(argv[2], "current_dirname")) { /* directory name of current design */
Tcl_SetResult(interp, xctx->current_dirname, TCL_VOLATILE);
}
- else if(!strcmp(argv[2], "current_name")) {
+ else if(!strcmp(argv[2], "current_name")) { /* name of current design (no library path) */
Tcl_SetResult(interp, xctx->current_name, TCL_VOLATILE);
}
- else if(!strcmp(argv[2], "current_win_path")) {
+ else if(!strcmp(argv[2], "current_win_path")) { /* path of current tab/window (.drw, .x1.drw, ...) */
Tcl_SetResult(interp, xctx->current_win_path, TCL_VOLATILE);
}
- else if(!strcmp(argv[2], "currsch")) {
+ else if(!strcmp(argv[2], "currsch")) { /* hierarchy level of current schematic (start at 0) */
Tcl_SetResult(interp, my_itoa(xctx->currsch),TCL_VOLATILE);
}
break;
case 'd':
- if(!strcmp(argv[2], "debug_var")) {
+ if(!strcmp(argv[2], "debug_var")) { /* debug level (0 = no debug, 1, 2, 3,...) */
Tcl_SetResult(interp, my_itoa(debug_var),TCL_VOLATILE);
}
- else if(!strcmp(argv[2], "draw_window")) {
+ else if(!strcmp(argv[2], "draw_window")) { /* direct draw into window */
Tcl_SetResult(interp, my_itoa(xctx->draw_window),TCL_VOLATILE);
}
break;
case 'f':
- if(!strcmp(argv[2], "format")) {
+ if(!strcmp(argv[2], "format")) { /* alternate format attribute to use in netlist (or NULL) */
if(!xctx->format ) Tcl_SetResult(interp, "