75 lines
1.7 KiB
Awk
Executable File
75 lines
1.7 KiB
Awk
Executable File
#!/bin/sh
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# creates an edif port declaration netlist from a vhdl file
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# usage: make_edif.awk file.vhd
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# resulting netlist will be written in file.edif
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#
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# Warning:
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# can be used on vhdl entities that have std_logic/std_logic_vector
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# pins, any other types not recognized
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# Also, types and ranges must NOT be referenced in packages or
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# as constants/variables, if this is the case use the design_analyzer
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# "EDIF save as" facility
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#
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# stefan, 23052002
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awk '
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BEGIN{
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# get cell name
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cell=ARGV[1]
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sub(/\..*/,"",cell)
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sub(/.*\//,"",cell)
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outfile = cell ".edif"
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# write header
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print "(edif Synopsys_edif (edifVersion 2 0 0) (edifLevel 0)" >outfile
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print " (library DESIGNS (edifLevel 0)" >outfile
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print " (cell " cell " (cellType GENERIC)" >outfile
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print " (view Netlist_representation (viewType NETLIST)" >outfile
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print " (interface" >outfile
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}
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# do some clean up
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{
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$0=toupper($0)
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sub(":"," : ",$0)
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sub(/;.*/,"",$0)
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sub("\("," ( ",$0)
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sub("\)"," ) ",$0)
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}
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# parse only entity declaration
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($1=="ENTITY" && $2==cell && $3== "IS") { entity=1 }
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($1=="END" && $2==cell) { entity=0 }
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# print port list
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($0 ~ /^[ \t]*[A-Z0-9_]+[ \t]*:[ \t]* (IN|OUT|INOUT)[ \t]+STD_LOGIC/ && entity){
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if($0 ~ /STD_LOGIC_VECTOR/) {
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if($6 < $8) print "Warning, ascending bus: " $0
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for( i=$6; i>=$8 ; i-- ) {
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print " (port " $1 "_E2V_" i " (direction " dir($3) "))" > outfile
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}
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}
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else {
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print " (port " $1 " (direction " dir($3) "))" > outfile
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}
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}
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# write trailer
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END{
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print " )" >outfile
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print " )" >outfile
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print " )" >outfile
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print " )" >outfile
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print ")" >outfile
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}
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function dir(d) {
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if(d=="IN") return "INPUT"
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else if(d=="OUT") return "OUTPUT"
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else return "INOUT"
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}
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' $@
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