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xschem
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update tedax netlister with previous enhancements

This commit is contained in:
stefan schippers 2023-04-26 10:26:21 +02:00
parent 10441ef901
commit 7a16859702
5 changed files with 9 additions and 9 deletions
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2
src/spice_netlist.c
View File

@ -78,7 +78,7 @@ void hier_psprint(char **res, int what) /* netlister driver */
int flag;
/* for printing we process also symbols that have *_ignore attribute */
if(!xctx->sym[i].type || !xctx->sym[i].name || !xctx->sym[i].name[0]) continue; /* can not descend into */
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
if(what & 1) flag = check_lib(2, abs_path); /* noprint_libs */
else flag = check_lib(4, abs_path); /* nolist_libs */
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && flag)

8
src/tedax_netlist.c
View File

@ -91,10 +91,10 @@ static int tedax_block_netlist(FILE *fd, int i)
fprintf(fd, "\n# expanding symbol: %s # of pins=%d\n",
xctx->sym[i].name,xctx->sym[i].rects[PINLAYER] );
if(xctx->sym[i].base_name) fprintf(fd, "## sym_path: %s\n", abs_sym_path(xctx->sym[i].base_name, ""));
else fprintf(fd, "## sym_path: %s\n", abs_sym_path(xctx->sym[i].name, ""));
fprintf(fd, "## sch_path: %s\n", filename);
else fprintf(fd, "## sym_path: %s\n", sanitized_abs_sym_path(xctx->sym[i].name, ""));
fprintf(fd, "## sch_path: %s\n", sanitized_abs_sym_path(filename, ""));
fprintf(fd, "begin netlist v1 %s\n",skip_dir(xctx->sym[i].name));
fprintf(fd, "begin netlist v1 %s\n",sanitize(skip_dir(xctx->sym[i].name)));
print_tedax_subckt(fd, i);
my_strdup(_ALLOC_ID_, &extra, get_tok_value(xctx->sym[i].prop_ptr,"extra",0) );
@ -207,7 +207,7 @@ int global_tedax_netlist(int global) /* netlister driver */
{
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue;
if(!xctx->sym[i].type) continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
{
tclvareval("get_directory [list ", xctx->sch[xctx->currsch - 1], "]", NULL);

4
src/token.c
View File

@ -1574,7 +1574,7 @@ void print_tedax_subckt(FILE *fd, int symbol)
for(i=0;i<no_of_pins; ++i)
{
if(strcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"spice_ignore",0), "true")) {
if(strcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"tedax_ignore",0), "true")) {
str_ptr=
expandlabel(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"name",0), &multip);
fprintf(fd, "%s ", str_ptr);
@ -2107,7 +2107,7 @@ void print_tedax_element(FILE *fd, int inst)
int n;
Int_hashtable table={NULL, 0};
subcircuit = 1;
fprintf(fd, "__subcircuit__ %s %s\n", get_sym_name(inst, 0), xctx->inst[inst].instname);
fprintf(fd, "__subcircuit__ %s %s\n", sanitize(get_sym_name(inst, 0)), xctx->inst[inst].instname);
int_hash_init(&table, 37);
for(i=0;i<no_of_pins; ++i) {
my_strdup2(_ALLOC_ID_, &net, net_name(inst,i, &net_mult, 0, 1));

2
src/verilog_netlist.c
View File

@ -356,7 +356,7 @@ int global_verilog_netlist(int global) /* netlister driver */
{
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(!xctx->sym[i].type) continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path)) {
tclvareval("get_directory [list ", xctx->sch[xctx->currsch - 1], "]", NULL);
my_strncpy(xctx->current_dirname, tclresult(), S(xctx->current_dirname));

2
src/vhdl_netlist.c
View File

@ -344,7 +344,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
strcmp(xctx->sym[j].type,"subcircuit")!=0)) continue;
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[j].name, ""));
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[j].name), ""));
if((
strcmp(xctx->sym[j].type,"subcircuit")==0 ||
strcmp(xctx->sym[j].type,"primitive")==0