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documentation updates for spectre netlisting related attributes and usage of @model in subcircuit format string as alternative to @symname

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stefan schippers 2025-07-21 10:41:45 +02:00
parent 6f6f4a3028
commit 720bf93a73
11 changed files with 73 additions and 18 deletions
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13
doc/xschem_man/component_property_syntax.html
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@ -161,7 +161,8 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
<li><kbd>spice_ignore</kbd></li>
<li><kbd>verilog_ignore</kbd></li>
<li><kbd>tedax_ignore</kbd></li>
<p >These 4 attributes tell XSCHEM to ignore completely the instance in the respective netlist formats.
<li><kbd>spectre_ignore</kbd></li>
<p >These 5 attributes tell XSCHEM to ignore completely the instance in the respective netlist formats.
Allowed values for these attributes are <kbd>true</kbd> (or <kbd>open</kbd>), <kbd>false</kbd> and
<kbd>short</kbd>
If <kbd>short</kbd> is specified the instance will short together all its pins. For this to work
@ -193,6 +194,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
<li><kbd>spice_sym_def</kbd></li>
<li><kbd>verilog_sym_def</kbd></li>
<li><kbd>vhdl_sym_def</kbd></li>
<li><kbd>spectre_sym_def</kbd></li>
<p> If any of these attributes are present and not empty and the symbol type is set to <kbd>subcircuit</kbd>
the corresponding netlister will ignore the schematic subcircuit for this specific instance
and dump into the netlist the content of this attribute.
@ -251,6 +253,15 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
in the symbol if any.
</p>
<li><kbd>spectre_device_model</kbd></li>
<p>
This attribute contains a SPECTRE model or subckt specification
(<kbd>spectre_device_model="model D1N4148 ...."</kbd>)
that will be printed at end of netlist only once for the specified component (D1N4148 in the example).
<kbd>spectre_device_model</kbd> attributes defined at instance level override the <kbd>spectre_device_model</kbd> set
in the symbol if any.
</p>
<li><kbd>schematic</kbd></li>
<p>
This attribute specifies an alternate schematic file to open when descending into the subcircuit.

16
doc/xschem_man/creating_symbols.html
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@ -54,7 +54,21 @@ p{padding: 15px 30px 10px;}
type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
</pre>
</pre><br>
<p class="important">
It is now possible to use @model instead of @symname to use a custom specified subcircuit name instead
of the symbol filename, see the following example for an opamp subcircuit with a gain parameter:
</p><br>
<pre class="code"style="width:500px;margin-left:40px;">
type=subcircuit
format="@name @pinlist @model gain=@gain"
template="name=x1 gain=100 model=opamp"
</pre><br>
<p> the above extension is allowed only for spice and spectre netlists.</p>
<p>
These attributes are using by xschem to generate the subcircuit netlist line. the <kbd>format</kbd>
attribute tells xschem that a line containing the instance name (<kbd>@name</kbd>, replaced by

7
doc/xschem_man/developer_info.html
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@ -92,7 +92,8 @@ p{padding: 15px 30px 10px;}
have a property string attached. Any text can be present in a property string, however
in most cases the property string is organized as a set of <kbd>key=value</kbd> pairs separated by white space.
In addition to object properties the schematic or symbol view has global properties attached.
There is one global property defined per netlisting mode (currently SPICE, VHDL, Verilog, tEDAx) and one additional global property
There is one global property defined per netlisting mode (currently SPICE, VHDL, Verilog, tEDAx, Spectre)
and one additional global property
for symbols (containing the netlisting rules usually).
See the <a href="xschem_properties.html">XSCHEM properties</a> section of the manual for more info.
</p>
@ -226,7 +227,7 @@ template="name=U1 footprint=TO220"}</kbd>
<p>
Global properties define a property string bound to the parent schematic/symbol file,
there is one global property record per netlisting mode,
currently SPICE, VHDL, Verilog, tEDAx.<br>
currently SPICE, VHDL, Verilog, tEDAx, Spectre.<br>
In addition (only in file_format 1.2 and newer) for schematics and symbols there is a global attribute ('K')
that defines how to netlist the schematic/symbol if placed as a
symbol into another parent schematic (should be set in the same way as the 'G' global attribute for symbols
@ -807,6 +808,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
<li><kbd> schprop </kbd> get schematic "spice" global attributes </li>
<li><kbd> schvhdlprop </kbd> get schematic "vhdl" global attributes </li>
<li><kbd> schverilogprop </kbd> get schematic "verilog" global attributes </li>
<li><kbd> schspectreprop </kbd> get schematic "spectre" global attributes </li>
<li><kbd> schsymbolprop </kbd> get schematic "symbol" global attributes </li>
<li><kbd> schtedaxprop </kbd> get schematic "tedax" global attributes </li>
<li><kbd> sch_path </kbd> get hierarchy path. if 'n' given get hierpath of level 'n' </li>
@ -1505,6 +1507,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
<li><kbd> schsymbolprop </kbd> set global symbol attribute string </li>
<li><kbd> schprop </kbd> set schematic global spice attribute string </li>
<li><kbd> schverilogprop </kbd> set schematic global verilog attribute string </li>
<li><kbd> schspectreprop </kbd> set schematic global spectre attribute string </li>
<li><kbd> schvhdlprop </kbd> set schematic global vhdl attribute string </li>
<li><kbd> schtedaxprop </kbd> set schematic global tedax attribute string </li>
<li><kbd> text_svg </kbd> set to 1 to use svg &lt;text&gt; elements </li>

6
doc/xschem_man/netlisting.html
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@ -21,9 +21,9 @@ p{padding: 15px 30px 10px;}
<!-- slide title -->
<h1>NETLISTING</h1><br>
<p>
XSCHEM has 3 predefined netlisting modes, <kbd>Spice</kbd>, <kbd>Verilog</kbd> and
XSCHEM has 4 predefined netlisting modes, <kbd>SPICE</kbd>, <kbd>Verilog</kbd>, <kbd>Spectre</kbd> and
<kbd>VHDL</kbd>. Netlisting mode can be set in the <kbd>Options</kbd> menu
(<kbd>Vhdl</kbd>, <kbd>Verilog</kbd> <kbd>Spice</kbd> radio buttons)
(<kbd>Vhdl</kbd>, <kbd>Verilog</kbd> <kbd>SPICE</kbd> <kbd>Spectre</kbd> radio buttons)
or with the <kbd>&lt;Shift&gt;V</kbd> key. Once a netlist mode is set, hitting the
<kbd>Netlist</kbd> button on the top-right of the menu bar or the <kbd>n</kbd>
key will produce the netlist file in the defined simulation directory.<br>
@ -118,7 +118,7 @@ format="@name @pinlist @symname"</pre>
<br>
<h3> Other netlist formats</h3>
<p>
All the concepts explained for SPICE netlist apply for Verilog and VHDL formats.
All the concepts explained for SPICE netlist apply for Verilog, Spectre and VHDL formats.
Its up to the designer to ensure that the objects in the schematic are 'known' to the
target simulator. For example a resistor is normally
not used in VHDL or Verilog designs, so unless an appropriate 'format'

34
doc/xschem_man/symbol_property_syntax.html
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@ -155,7 +155,8 @@ type=nmos
<li><kbd>spice_ignore</kbd></li>
<li><kbd>verilog_ignore</kbd></li>
<li><kbd>tedax_ignore</kbd></li>
<p>These 4 attributes tell XSCHEM to ignore completely all instances of the symbol in the respective netlist formats.
<li><kbd>spectre_ignore</kbd></li>
<p>These 5 attributes tell XSCHEM to ignore completely all instances of the symbol in the respective netlist formats.
Allowed values for these attributes are <kbd>true</kbd> (or <kbd>open</kbd>), <kbd>false</kbd> and
<kbd>short</kbd>
If <kbd>short</kbd> is specified all symbol instances will short together all their pins. For this to work
@ -182,6 +183,7 @@ type=nmos
<li><kbd>spice_stop</kbd></li>
<li><kbd>verilog_stop</kbd></li>
<li><kbd>tedax_stop</kbd></li>
<li><kbd>spectre_stop</kbd></li>
<p> These 4 attributes will avoid XSCHEM to descend into the schematic representation of the symbol
(if there is one) when building the respective netlist format. For example, if an analog block
has a schematic (.sch) file describing the circuit that is meaningless when doing a VHDL netlist,
@ -192,6 +194,7 @@ type=nmos
<li><kbd>spice_primitive</kbd></li>
<li><kbd>vhdl_primitive</kbd></li>
<li><kbd>verilog_primitive</kbd></li>
<li><kbd>spectre_primitive</kbd></li>
<p> Same as above <kbd>_stop</kbd> attributes, but in this case the schematic subcircuit is completely ignored,
only the 'format' string is dumped to netlist. No component/entity is generated in vhdl netlist,
no module declaration in verilog, no .subckt in spice, no schematic global attributes are exported to netlist.</p>
@ -204,6 +207,7 @@ type=nmos
<li><kbd>spice_sym_def</kbd></li>
<li><kbd>verilog_sym_def</kbd></li>
<li><kbd>vhdl_sym_def</kbd></li>
<li><kbd>spectre_sym_def</kbd></li>
<p> If any of these attributes are present and not empty and the symbol type is set to <kbd>subcircuit</kbd>
the corresponding netlister will ignore the schematic subcircuit
and dump into the netlist the content of this attribute. The typical usage is to include a file, example:<br>
@ -401,7 +405,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
for tEDAx netlists.
<br><br>
<li><kbd>sim_pinnumber</kbd></li>
For VHDL, SPICE, Verilog netlists: define the ordering of symbol ports in netlist.
For VHDL, SPICE, Verilog, Spectre netlists: define the ordering of symbol ports in netlist.
If all symbol pins have a sim_pinnumber attribute this symbol will be netlisted
(in all netlist formats) with pins sorted in ascending order according to sim_pinnumber value.
Start value of sim_pinnumber does not matter (may start at 1 or 0) , it is used as the sort key.
@ -496,8 +500,9 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
<li><kbd>spice_netlist</kbd></li>
<li><kbd>verilog_netlist</kbd></li>
<li><kbd>vhdl_netlist</kbd></li>
<li><kbd>spectre_netlist</kbd></li>
<p>
If any of these 3 properties if set to <kbd>true</kbd> the symbol will be netlisted in the specified format.
If any of these 4 properties if set to <kbd>true</kbd> the symbol will be netlisted in the specified format.
This is only valid if the split file netlisting mode is active (<kbd>Options -&gt; Split netlist</kbd>).
This is very rarely used but is required in mixed mode simulations, where part of the system will be
handled by an analog simulator (spice) and another part of the system by a digital Verilog / VHDL simulator.
@ -522,6 +527,12 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
This attribute contains a SPICE .model or .subckt specification (<kbd>device_model=".model D1N4148 D ...."</kbd>)
that will be printed at end of netlist only once for the specified component (D1N4148 in the example).
</p>
<li><kbd>spectre_device_model</kbd></li>
<p>
This attribute contains a SPECTRE model or subckt specification
(<kbd>spectre_device_model="model D1N4148 D ...."</kbd>)
that will be printed at end of netlist only once for the specified component (D1N4148 in the example).
</p>
<li><kbd>schematic</kbd></li>
<p>
This attribute specifies an alternate schematic file to open when descending into the subcircuit:
@ -566,6 +577,15 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
expands to <kbd>patternR2[2],patternR2[1],patternR2[0]</kbd><br>
<li><kbd>@symname</kbd></li>
<p> This expands to the name of the symbol</p>
<li><kbd>@model</kbd></li>
<p> This expands to the name of the symbol, instead of taking the filename it will use the <kbd>model</kbd>
attribute as defined in the template symbol attribute. This is possible for spice and spectre netlists only.
Example:<br>
<pre class="code">
type=subcircuit
format="@name @pinlist @model gain=@gain offset=@offset"
template="name=X1 model=opamp gain=100 offset=0" </pre>
</p>
<li><kbd>@symref</kbd></li>
<p> This expands to the symbol reference exactly as specified in the instance (the <kbd>Symbol</kbd> textbox
if you edit the symbol attributes with <kbd>q</kbd> key).</p>
@ -579,7 +599,7 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
the order they are set in the symbol</p>
<li><kbd>@@pin</kbd></li>
<p> This expands to the net that connect to symbol pin named <kbd>pin</kbd>. This substitution
takes place only when producing a netlist (Spice, Verilog, VHDL, tEDAx) so it is allowed to use this
takes place only when producing a netlist (Spice, Verilog, Spectre, VHDL, tEDAx) so it is allowed to use this
value only in <kbd>format</kbd>,<kbd>vhdl_format</kbd>, <kbd>tedax_format</kbd> or <kbd>verilog_format</kbd>
attributes (see <a href="netlisting.html">Netlisting slide)</a><br>
The @#pin attribute is expanded to <kbd>?m net</kbd> where <kbd>m</kbd> is the pin multiplicity and
@ -588,7 +608,7 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
<li><kbd>@#n</kbd></li>
<p>
This expands to the net that connect to symbol pin at position <kbd>n</kbd> in the XSCHEM internal storage. This substitution
takes place only when producing a netlist (Spice, Verilog, VHDL, tEDAx) so it is allowed to use this
takes place only when producing a netlist (Spice, Verilog, Spectre, VHDL, tEDAx) so it is allowed to use this
value only in <kbd>format</kbd>,<kbd>vhdl_format</kbd>, <kbd>tedax_format</kbd> or <kbd>verilog_format</kbd>
attributes (see <a href="netlisting.html">Netlisting slide)</a><br>
This method of accessing a net that connects to a pin is much faster than previous one since XSCHEM does not need to
@ -720,6 +740,10 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
<p>
this expands to the <b>Verilog</b> global property string of the schematic containing the symbol
</p>
<li><kbd>@schspectreprop</kbd></li>
<p>
this expands to the <b>Spectre</b> global property string of the schematic containing the symbol
</p>
</ul><br>
<h3>TCL ATTRIBUTE SUBSTITUTION</h3>

5
doc/xschem_man/tutorial_instance_based_implementation.html
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@ -107,8 +107,9 @@ spice_sym_def=".include /path/to/subckt_file" </pre>
</p><br><br>
<p class="important">
Note: all the above concepts are valid for VHDL, Verilog and tEDAx netlists by replacing the
<kbd>spice_sym_def</kbd> attribute with <kbd>vhdl_sym_def</kbd>, <kbd>verilog_sym_def</kbd> and <kbd>tedax_sym_def</kbd>
Note: all the above concepts are valid for VHDL, Verilog, Spectre and tEDAx netlists by replacing the
<kbd>spice_sym_def</kbd> attribute with <kbd>vhdl_sym_def</kbd>, <kbd>verilog_sym_def</kbd>,
<kbd>spectre_sym_def</kbd> and <kbd>tedax_sym_def</kbd>
respectively.
</p><br><br>

2
doc/xschem_man/tutorial_xschem_slides.html
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@ -25,7 +25,7 @@ p{padding: 15px 30px 10px;}
<h3 style="text-align:left; max-width: 70%;margin-left:0;">
<ul style="margin-left:0;">
<li>Hierarchical representation of circuits.</li>
<li>Generate circuit netlists for SPICE, Verilog, VHDL, <br>tEDAx (pcb-rnd interchange format)</li>
<li>Generate circuit netlists for SPICE, Verilog, VHDL, Spectre, <br>tEDAx (pcb-rnd interchange format)</li>
<li>Components can be primitives, behavioral blocks, subcircuit blocks.</li>
<li>True mixed mode circuit description: Analog, Behavioral, Transistor-level, Gate-level.</li>
<li>Designed from ground-up to handle Very large designs as efficiently as possible, no scripting language is used for intensive computations.</li>

2
doc/xschem_man/tutorial_xschem_slides04.html
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@ -33,7 +33,7 @@ p{padding: 15px 30px 10px;}
<li>Fast: Performance is important. Editing a schematic with 100K instances MUST not be a problem.
Netlist extraction must be instant (&lt;500ms) on small to medium designs.</li>
<li>Xschem knows the connectivity. Netlist build is embedded in the core.</li>
<li>Verilog, VHDL, Spice, tEDAx netlist backends. Adding another backend is not difficult.</li>
<li>Verilog, VHDL, SPICE, Spectre, tEDAx netlist backends. Adding another backend is not difficult.</li>
<li>Intensive and time consuming computations all done in pure C.</li>
<li>Tcl-tk used for GUI and scripting language. Direct Xlib drawing.</li>
</ul>

3
doc/xschem_man/tutorial_xschem_slides05.html
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@ -32,7 +32,8 @@ p{padding: 15px 30px 10px;}
<tr><td>Memory footprint.</td><td>Very low, data purged on hierarchy traversal.</td></tr>
<tr><td>Undo buffer.</td><td>Yes.</td></tr>
<tr><td>Scripting language / GUI toolkit</td><td>Tcl / Tk.</td></tr>
<tr><td>Schematic netlisting.</td><td>SPICE, Verilog, VHDL, tEDAx, embedded into XSCHEM and using Awk post processors.</td></tr>
<tr><td>Schematic netlisting.</td><td>SPICE, Verilog, VHDL, Spectre, tEDAx, embedded into XSCHEM and
using Awk post processors.</td></tr>
<tr><td>Wire snap to pin.</td><td>Yes.</td></tr>
<tr><td>Instance pin auto wiring.</td><td>Yes.</td></tr>
<tr><td>Net auto-router engine.</td><td>No.</td></tr>

1
doc/xschem_man/tutorial_xschem_slides08.html
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@ -41,6 +41,7 @@ th,td {font-size: 60%;padding: 3px;}
<table style="float: left;margin-top:10px;margin-bottom: 10px;">
<tr><th>TOOL</th><th>TYPE</th><th>XSCHEM<br>SUPPORT</th></tr>
<tr><td>VACASK</td><td>Simulator</td><td>Works</td></tr>
<tr><td>Hspice</td><td>Proprietary<br>Simulator</td><td>Works</td></tr>
<tr><td>Finesim</td><td>Proprietary<br>Simulator</td><td>Works</td></tr>
<tr><td>Gtkwave</td><td>Viewer</td><td>Works</td></tr>

2
doc/xschem_man/tutorial_xschem_slides081.html
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@ -31,7 +31,7 @@ p{padding: 15px 30px 10px;}
<li> Tools can be run in the background. Xschem optionally shows exit status, stderr and stdout
messages from batch jobs without blocking.</li>
<li> Multiple Simulator / viewing tools can be configured for each simulation mode
(spice, VHDL, Verilog), a radio button sets the active tool.</li>
(spice, VHDL, Verilog, Spectre), a radio button sets the active tool.</li>
<li> Additional tools (logic synthesis, etc) can easily be added in the future.</li>
<li> No information about external tools is hard coded in Xschem.</li>
</ul>