diff --git a/doc/xschem_man/component_property_syntax.html b/doc/xschem_man/component_property_syntax.html index 75acf5a2..199f3754 100644 --- a/doc/xschem_man/component_property_syntax.html +++ b/doc/xschem_man/component_property_syntax.html @@ -161,7 +161,8 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
  • spice_ignore
  • verilog_ignore
  • tedax_ignore
    • -

    These 4 attributes tell XSCHEM to ignore completely the instance in the respective netlist formats. +

  • spectre_ignore
    • +

    These 5 attributes tell XSCHEM to ignore completely the instance in the respective netlist formats. Allowed values for these attributes are true (or open), false and short If short is specified the instance will short together all its pins. For this to work @@ -193,6 +194,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"

  • spice_sym_def
  • verilog_sym_def
  • vhdl_sym_def
    • +
  • spectre_sym_def

    • If any of these attributes are present and not empty and the symbol type is set to subcircuit the corresponding netlister will ignore the schematic subcircuit for this specific instance and dump into the netlist the content of this attribute. @@ -251,6 +253,15 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10" in the symbol if any.

    +
  • spectre_device_model
    • +

    + This attribute contains a SPECTRE model or subckt specification + (spectre_device_model="model D1N4148 ....") + that will be printed at end of netlist only once for the specified component (D1N4148 in the example). + spectre_device_model attributes defined at instance level override the spectre_device_model set + in the symbol if any. +

    +
  • schematic

    • This attribute specifies an alternate schematic file to open when descending into the subcircuit. diff --git a/doc/xschem_man/creating_symbols.html b/doc/xschem_man/creating_symbols.html index b77bf05b..976b7a1e 100644 --- a/doc/xschem_man/creating_symbols.html +++ b/doc/xschem_man/creating_symbols.html @@ -54,7 +54,21 @@ p{padding: 15px 30px 10px;} type=subcircuit format="@name @pinlist @symname" template="name=x1" - +
    + +

    + It is now possible to use @model instead of @symname to use a custom specified subcircuit name instead + of the symbol filename, see the following example for an opamp subcircuit with a gain parameter: +


    + + 
    +type=subcircuit
+format="@name @pinlist @model gain=@gain"
+template="name=x1 gain=100 model=opamp"
+

    + +

    the above extension is allowed only for spice and spectre netlists.

    +

    These attributes are using by xschem to generate the subcircuit netlist line. the format attribute tells xschem that a line containing the instance name (@name, replaced by diff --git a/doc/xschem_man/developer_info.html b/doc/xschem_man/developer_info.html index 587186bc..6feda0eb 100644 --- a/doc/xschem_man/developer_info.html +++ b/doc/xschem_man/developer_info.html @@ -92,7 +92,8 @@ p{padding: 15px 30px 10px;} have a property string attached. Any text can be present in a property string, however in most cases the property string is organized as a set of key=value pairs separated by white space. In addition to object properties the schematic or symbol view has global properties attached. - There is one global property defined per netlisting mode (currently SPICE, VHDL, Verilog, tEDAx) and one additional global property + There is one global property defined per netlisting mode (currently SPICE, VHDL, Verilog, tEDAx, Spectre) + and one additional global property for symbols (containing the netlisting rules usually). See the XSCHEM properties section of the manual for more info.

    @@ -226,7 +227,7 @@ template="name=U1 footprint=TO220"}

    Global properties define a property string bound to the parent schematic/symbol file, there is one global property record per netlisting mode, - currently SPICE, VHDL, Verilog, tEDAx.
    + currently SPICE, VHDL, Verilog, tEDAx, Spectre.
    In addition (only in file_format 1.2 and newer) for schematics and symbols there is a global attribute ('K') that defines how to netlist the schematic/symbol if placed as a symbol into another parent schematic (should be set in the same way as the 'G' global attribute for symbols @@ -807,6 +808,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"

  • schprop get schematic "spice" global attributes
  • schvhdlprop get schematic "vhdl" global attributes
  • schverilogprop get schematic "verilog" global attributes
    • +
  • schspectreprop get schematic "spectre" global attributes
  • schsymbolprop get schematic "symbol" global attributes
  • schtedaxprop get schematic "tedax" global attributes
  • sch_path get hierarchy path. if 'n' given get hierpath of level 'n'
    • @@ -1505,6 +1507,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
  • schsymbolprop set global symbol attribute string
  • schprop set schematic global spice attribute string
  • schverilogprop set schematic global verilog attribute string
    • +
  • schspectreprop set schematic global spectre attribute string
  • schvhdlprop set schematic global vhdl attribute string
  • schtedaxprop set schematic global tedax attribute string
  • text_svg set to 1 to use svg <text> elements
    • diff --git a/doc/xschem_man/netlisting.html b/doc/xschem_man/netlisting.html index 19adf4cb..47cd6089 100644 --- a/doc/xschem_man/netlisting.html +++ b/doc/xschem_man/netlisting.html @@ -21,9 +21,9 @@ p{padding: 15px 30px 10px;}

    NETLISTING


    - XSCHEM has 3 predefined netlisting modes, Spice, Verilog and + XSCHEM has 4 predefined netlisting modes, SPICE, Verilog, Spectre and VHDL. Netlisting mode can be set in the Options menu - (Vhdl, Verilog Spice radio buttons) + (Vhdl, Verilog SPICE Spectre radio buttons) or with the <Shift>V key. Once a netlist mode is set, hitting the Netlist button on the top-right of the menu bar or the n key will produce the netlist file in the defined simulation directory.
    @@ -118,7 +118,7 @@ format="@name @pinlist @symname"

    Other netlist formats

    - All the concepts explained for SPICE netlist apply for Verilog and VHDL formats. + All the concepts explained for SPICE netlist apply for Verilog, Spectre and VHDL formats. Its up to the designer to ensure that the objects in the schematic are 'known' to the target simulator. For example a resistor is normally not used in VHDL or Verilog designs, so unless an appropriate 'format' diff --git a/doc/xschem_man/symbol_property_syntax.html b/doc/xschem_man/symbol_property_syntax.html index 5ff5abce..028e84cd 100644 --- a/doc/xschem_man/symbol_property_syntax.html +++ b/doc/xschem_man/symbol_property_syntax.html @@ -155,7 +155,8 @@ type=nmos

  • spice_ignore
  • verilog_ignore
  • tedax_ignore
    • -

    These 4 attributes tell XSCHEM to ignore completely all instances of the symbol in the respective netlist formats. +

  • spectre_ignore
    • +

    These 5 attributes tell XSCHEM to ignore completely all instances of the symbol in the respective netlist formats. Allowed values for these attributes are true (or open), false and short If short is specified all symbol instances will short together all their pins. For this to work @@ -182,6 +183,7 @@ type=nmos

  • spice_stop
  • verilog_stop
  • tedax_stop
    • +
  • spectre_stop

    • These 4 attributes will avoid XSCHEM to descend into the schematic representation of the symbol (if there is one) when building the respective netlist format. For example, if an analog block has a schematic (.sch) file describing the circuit that is meaningless when doing a VHDL netlist, @@ -192,6 +194,7 @@ type=nmos

  • spice_primitive
  • vhdl_primitive
  • verilog_primitive
    • +
  • spectre_primitive

    • Same as above _stop attributes, but in this case the schematic subcircuit is completely ignored, only the 'format' string is dumped to netlist. No component/entity is generated in vhdl netlist, no module declaration in verilog, no .subckt in spice, no schematic global attributes are exported to netlist.

    @@ -204,6 +207,7 @@ type=nmos
  • spice_sym_def
  • verilog_sym_def
  • vhdl_sym_def
    • +
  • spectre_sym_def

    • If any of these attributes are present and not empty and the symbol type is set to subcircuit the corresponding netlister will ignore the schematic subcircuit and dump into the netlist the content of this attribute. The typical usage is to include a file, example:
    @@ -401,7 +405,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1 for tEDAx netlists.

  • sim_pinnumber
    • - For VHDL, SPICE, Verilog netlists: define the ordering of symbol ports in netlist. + For VHDL, SPICE, Verilog, Spectre netlists: define the ordering of symbol ports in netlist. If all symbol pins have a sim_pinnumber attribute this symbol will be netlisted (in all netlist formats) with pins sorted in ascending order according to sim_pinnumber value. Start value of sim_pinnumber does not matter (may start at 1 or 0) , it is used as the sort key. @@ -496,8 +500,9 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
  • spice_netlist
  • verilog_netlist
  • vhdl_netlist
    • +
  • spectre_netlist

    • - If any of these 3 properties if set to true the symbol will be netlisted in the specified format. + If any of these 4 properties if set to true the symbol will be netlisted in the specified format. This is only valid if the split file netlisting mode is active (Options -> Split netlist). This is very rarely used but is required in mixed mode simulations, where part of the system will be handled by an analog simulator (spice) and another part of the system by a digital Verilog / VHDL simulator. @@ -522,6 +527,12 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );" This attribute contains a SPICE .model or .subckt specification (device_model=".model D1N4148 D ....") that will be printed at end of netlist only once for the specified component (D1N4148 in the example).

    +
  • spectre_device_model
    • +

    + This attribute contains a SPECTRE model or subckt specification + (spectre_device_model="model D1N4148 D ....") + that will be printed at end of netlist only once for the specified component (D1N4148 in the example). +

  • schematic

    • This attribute specifies an alternate schematic file to open when descending into the subcircuit: @@ -566,6 +577,15 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );" expands to patternR2[2],patternR2[1],patternR2[0]

  • @symname

    • This expands to the name of the symbol

    +
  • @model
    • +

    This expands to the name of the symbol, instead of taking the filename it will use the model + attribute as defined in the template symbol attribute. This is possible for spice and spectre netlists only. + Example:
    + 

    +     type=subcircuit
+     format="@name @pinlist @model gain=@gain offset=@offset"
+     template="name=X1 model=opamp gain=100 offset=0"
    +

  • @symref

    • This expands to the symbol reference exactly as specified in the instance (the Symbol textbox if you edit the symbol attributes with q key).

    @@ -579,7 +599,7 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );" the order they are set in the symbol

  • @@pin

    • This expands to the net that connect to symbol pin named pin. This substitution - takes place only when producing a netlist (Spice, Verilog, VHDL, tEDAx) so it is allowed to use this + takes place only when producing a netlist (Spice, Verilog, Spectre, VHDL, tEDAx) so it is allowed to use this value only in format,vhdl_format, tedax_format or verilog_format attributes (see Netlisting slide)
    The @#pin attribute is expanded to ?m net where m is the pin multiplicity and @@ -588,7 +608,7 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"

  • @#n

    • This expands to the net that connect to symbol pin at position n in the XSCHEM internal storage. This substitution - takes place only when producing a netlist (Spice, Verilog, VHDL, tEDAx) so it is allowed to use this + takes place only when producing a netlist (Spice, Verilog, Spectre, VHDL, tEDAx) so it is allowed to use this value only in format,vhdl_format, tedax_format or verilog_format attributes (see Netlisting slide)
    This method of accessing a net that connects to a pin is much faster than previous one since XSCHEM does not need to @@ -720,6 +740,10 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"

    this expands to the Verilog global property string of the schematic containing the symbol

    +
  • @schspectreprop
    • +

    + this expands to the Spectre global property string of the schematic containing the symbol +


    TCL ATTRIBUTE SUBSTITUTION

    diff --git a/doc/xschem_man/tutorial_instance_based_implementation.html b/doc/xschem_man/tutorial_instance_based_implementation.html index 3ea2b8d4..48e7acb8 100644 --- a/doc/xschem_man/tutorial_instance_based_implementation.html +++ b/doc/xschem_man/tutorial_instance_based_implementation.html @@ -107,8 +107,9 @@ spice_sym_def=".include /path/to/subckt_file"



    - Note: all the above concepts are valid for VHDL, Verilog and tEDAx netlists by replacing the - spice_sym_def attribute with vhdl_sym_def, verilog_sym_def and tedax_sym_def + Note: all the above concepts are valid for VHDL, Verilog, Spectre and tEDAx netlists by replacing the + spice_sym_def attribute with vhdl_sym_def, verilog_sym_def, + spectre_sym_def and tedax_sym_def respectively.



    diff --git a/doc/xschem_man/tutorial_xschem_slides.html b/doc/xschem_man/tutorial_xschem_slides.html index 6a81d6e2..dd5bcf02 100644 --- a/doc/xschem_man/tutorial_xschem_slides.html +++ b/doc/xschem_man/tutorial_xschem_slides.html @@ -25,7 +25,7 @@ p{padding: 15px 30px 10px;}

    diff --git a/doc/xschem_man/tutorial_xschem_slides05.html b/doc/xschem_man/tutorial_xschem_slides05.html index eb0f3bbc..4f05ecbb 100644 --- a/doc/xschem_man/tutorial_xschem_slides05.html +++ b/doc/xschem_man/tutorial_xschem_slides05.html @@ -32,7 +32,8 @@ p{padding: 15px 30px 10px;} Memory footprint.Very low, data purged on hierarchy traversal. Undo buffer.Yes. Scripting language / GUI toolkitTcl / Tk. - Schematic netlisting.SPICE, Verilog, VHDL, tEDAx, embedded into XSCHEM and using Awk post processors. + Schematic netlisting.SPICE, Verilog, VHDL, Spectre, tEDAx, embedded into XSCHEM and + using Awk post processors. Wire snap to pin.Yes. Instance pin auto wiring.Yes. Net auto-router engine.No. diff --git a/doc/xschem_man/tutorial_xschem_slides08.html b/doc/xschem_man/tutorial_xschem_slides08.html index a8863da2..8495d46f 100644 --- a/doc/xschem_man/tutorial_xschem_slides08.html +++ b/doc/xschem_man/tutorial_xschem_slides08.html @@ -41,6 +41,7 @@ th,td {font-size: 60%;padding: 3px;} + diff --git a/doc/xschem_man/tutorial_xschem_slides081.html b/doc/xschem_man/tutorial_xschem_slides081.html index 426ac056..e18e6c0b 100644 --- a/doc/xschem_man/tutorial_xschem_slides081.html +++ b/doc/xschem_man/tutorial_xschem_slides081.html @@ -31,7 +31,7 @@ p{padding: 15px 30px 10px;}
  • Tools can be run in the background. Xschem optionally shows exit status, stderr and stdout messages from batch jobs without blocking.
  • Multiple Simulator / viewing tools can be configured for each simulation mode - (spice, VHDL, Verilog), a radio button sets the active tool.
    • + (spice, VHDL, Verilog, Spectre), a radio button sets the active tool.
  • Additional tools (logic synthesis, etc) can easily be added in the future.
  • No information about external tools is hard coded in Xschem.
    • TOOLTYPEXSCHEM
    SUPPORT
    VACASKSimulatorWorks
    HspiceProprietary
    Simulator    		Works
    FinesimProprietary
    Simulator    		Works
    GtkwaveViewerWorks