spice netlists: allow specifying a prefix to symbol pins, like: #~#@@A[3:0] --> will expand to ~A[3],~A[2],~A[1],~A[0] and then unrolled into individual instances as usual with spice netlists.
This commit is contained in:
stefan schippers
parent
064c923cac
commit
5d5a4adbfd
147
src/spice.awk
147
src/spice.awk
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@ -211,13 +211,24 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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sub(/^#/,"",iprefix)
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sub(/#.*/,"",iprefix)
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sub("#" iprefix "#", iprefix,$i)
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gsub(/,/, "," iprefix,$i)
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gsub(/,/, "," iprefix, $i)
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## 20160301 add '?1' if missing in format string
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if(i>1 && ( $(i-1) !~/^\?/) ) {
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$i = "?1 " $i
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}
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$0 = $0 # reparse input line
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}
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# prefix applied to symbol pin, like for example prepending negation operator '~' to pin:
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# format= ... #~#@@A[3:0] --> #~#?4 A[3],A[2],A[1],A[0] --> ~A[3],~A[2],~A[1],~A[0]
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if($i ~/^#[~a-zA-Z_0-9]+#\?/) {
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iprefix=$i
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sub(/^#/,"",iprefix)
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sub(/#.*/,"",iprefix)
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sub("#" iprefix "#", "",$i)
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$(i+1) = iprefix $(i+1)
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gsub(/,/, "," iprefix, $(i+1))
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$0 = $0 # reparse input line
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}
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}
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## 20140506 do not transform {} of variation groups
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## nmos N {
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@ -274,76 +285,76 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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}
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}
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#### this is never executed: commented lines are processed and skipped above
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# } else if( $1 ~ /^\*\.(ipin|opin|iopin)/ ) {
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# num=split($2,name,",")
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# for(i=1;i<=num;i++) print $1 " " name[i]
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} else if( tolower($1) ~ /\.subckt/) {
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# remove m=.. from subcircuit definition since m= is a multiplier not a param
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sub(/ m=[0-9]+/," ",$0)
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gsub(","," ",$0)
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print $0
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} else {
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# handle uncommon primitives that have a prefix before the device name
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if(tolower($1) in special_devs) {
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# YDELAY ?1 Rda[4],Rda[3],Rda[2],Rda[1],Rda[0] ?1 softrst[4],softrst[3],...
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devprefix = $1
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num = split($3, name, ",")
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$1 = ""
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for(i = 0; i < num; i++) {
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if(i) $1 = $1 ","
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$1 = $1 devprefix
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}
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num = split($1, name, ",")
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$0 = $0
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#### this is never executed: commented lines are processed and skipped above
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# } else if( $1 ~ /^\*\.(ipin|opin|iopin)/ ) {
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# num=split($2,name,",")
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# for(i=1;i<=num;i++) print $1 " " name[i]
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} else if( tolower($1) ~ /\.subckt/) {
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# remove m=.. from subcircuit definition since m= is a multiplier not a param
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sub(/ m=[0-9]+/," ",$0)
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gsub(","," ",$0)
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print $0
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} else {
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num = split($1, name, ",")
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}
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if(num==0) print ""
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for(j=2;j<=NF;j+=1) # start from 2 not from 3 20070221
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{
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# ............ --> matches ?n and ?-n
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# some CDL netlists have this: $SUB=?1 B where B is a node
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if($j ~/^(.*=)?\?-?[0-9]+$/) continue # handle the case that $2 not pinlist 20070221
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arg_num[j]=split($j,tmp,",")
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for(k=1;k<=arg_num[j]; k++) {
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arg_name[j,k]=tmp[k]
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}
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}
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for(i=1;i<=num;i++)
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{
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printf "%s ", spiceprefix name[i]
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for(j=2;j<=NF;j++)
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{
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# ............ --> matches ?n and ?-n
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# some CDL netlists have this: $SUB=?1 B where B is a node
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if($j !~ /^(.*=)?\?-?[0-9]+$/)
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{
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printf "%s ", $j # if not a node just print it
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}
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else
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{
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nmult=$(j)
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if(nmult ~ /^(.*=)/) { # some CDL netlists have this: $SUB=?1 B where B is a node
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sub(/=.*/, "=", nmult)
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printf "%s", nmult
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# handle uncommon primitives that have a prefix before the device name
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if(tolower($1) in special_devs) {
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# YDELAY ?1 Rda[4],Rda[3],Rda[2],Rda[1],Rda[0] ?1 softrst[4],softrst[3],...
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devprefix = $1
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num = split($3, name, ",")
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$1 = ""
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for(i = 0; i < num; i++) {
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if(i) $1 = $1 ","
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$1 = $1 devprefix
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}
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nmult=$(j++)
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sub(/(.*=)?\?/,"",nmult)
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if(nmult+0==-1) nmult=arg_num[j]
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for(l=0;l<nmult+0;l++)
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{
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ii=(l+nmult*(i-1))%arg_num[j]+1
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printf "%s ", arg_name[j,ii]
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}
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}
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num = split($1, name, ",")
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$0 = $0
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} else {
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num = split($1, name, ",")
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}
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if(num==0) print ""
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for(j=2;j<=NF;j+=1) # start from 2 not from 3 20070221
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{
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# ............ --> matches ?n and ?-n
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# some CDL netlists have this: $SUB=?1 B where B is a node
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if($j ~/^(.*=)?\?-?[0-9]+$/) continue # handle the case that $2 not pinlist 20070221
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arg_num[j]=split($j,tmp,",")
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for(k=1;k<=arg_num[j]; k++) {
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arg_name[j,k]=tmp[k]
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}
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}
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for(i=1;i<=num;i++)
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{
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printf "%s ", spiceprefix name[i]
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for(j=2;j<=NF;j++)
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{
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# ............ --> matches ?n and ?-n
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# some CDL netlists have this: $SUB=?1 B where B is a node
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if($j !~ /^(.*=)?\?-?[0-9]+$/)
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{
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printf "%s ", $j # if not a node just print it
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}
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else
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{
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nmult=$(j)
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if(nmult ~ /^(.*=)/) { # some CDL netlists have this: $SUB=?1 B where B is a node
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sub(/=.*/, "=", nmult)
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printf "%s", nmult
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}
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nmult=$(j++)
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sub(/(.*=)?\?/,"",nmult)
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if(nmult+0==-1) nmult=arg_num[j]
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for(l=0;l<nmult+0;l++)
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{
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ii=(l+nmult*(i-1))%arg_num[j]+1
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printf "%s ", arg_name[j,ii]
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}
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}
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}
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printf "\n"
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}
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printf "\n"
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}
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}
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}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -21,9 +21,11 @@ v {xschem version=3.4.4 file_version=1.2
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}
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G {
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Y <= not (not A) after delay ;}
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K {}
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V {assign #del Y=A;
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}
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S {}
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F {}
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E {}
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C {opin.sym} 670 -290 0 0 {name=p0 lab=Y}
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C {ipin.sym} 250 -290 0 0 {name=p3 lab=A}
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@ -37,3 +39,5 @@ library ieee;
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-- use SYNOPSYS.ATTRIBUTES.ALL;
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}
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C {title.sym} 160 -30 0 0 {name=l2}
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C {noconn.sym} 670 -290 0 0 {name=l1}
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C {noconn.sym} 250 -290 0 1 {name=l3}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -21,9 +21,11 @@ v {xschem version=3.4.4 file_version=1.2
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}
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G {
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Y <= A xor B after delay ;}
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K {}
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V {
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assign #del Y=A^B;}
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S {}
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F {}
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E {}
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C {ipin.sym} 150 -320 0 0 {name=p2 lab=A}
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C {ipin.sym} 150 -350 0 0 {name=p3 lab=B}
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@ -38,3 +40,6 @@ library ieee;
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-- use SYNOPSYS.ATTRIBUTES.ALL;
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}
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C {title.sym} 160 -30 0 0 {name=l2}
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C {noconn.sym} 920 -350 0 0 {name=l1}
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C {noconn.sym} 150 -350 0 1 {name=l3}
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C {noconn.sym} 150 -320 0 1 {name=l4}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -30,6 +30,7 @@ end if ;
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end process ;
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}
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K {}
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V {reg iQ;
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always @(posedge CK or posedge RST) begin
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if(RST) iQ=0;
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@ -39,6 +40,7 @@ end
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assign #del Q=iQ;
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}
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S {}
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F {}
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E {}
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C {ipin.sym} 60 -150 0 0 {name=p1 lab=D}
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C {opin.sym} 130 -130 0 0 {name=p2 verilog_type=wire lab=Q}
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@ -49,3 +51,7 @@ C {use.sym} 100 -440 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;}
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C {noconn.sym} 130 -130 0 0 {name=l1}
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C {noconn.sym} 60 -150 0 1 {name=l3}
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C {noconn.sym} 60 -130 0 1 {name=l4}
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C {noconn.sym} 60 -110 0 1 {name=l5}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {type=subcircuit
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G {}
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K {type=subcircuit
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vhdl_stop=true
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verilog_stop=true
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format="@name @pinlist @symname"
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@ -27,6 +28,7 @@ template="name=x1 delay=\\"400 ps\\" del=400"
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generic_type="delay=time"}
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V {}
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S {}
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F {}
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E {}
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L 4 -50 -30 50 -30 {}
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L 4 -50 30 50 30 {}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -93,6 +93,7 @@ assign #oe_delay DOUT = OEN ? 'bz: iidata;
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}
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S {}
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F {}
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E {}
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L 4 290 -560 290 -260 {}
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L 4 210 -560 210 -260 {}
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@ -180,3 +181,4 @@ C {arch_declarations.sym} 750 -630 0 0 { constant RAM_DEPTH :integer := 2**di
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signal mem : RAMARR (0 to RAM_DEPTH-1);
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signal data : std_logic_vector(width-1 downto 0);
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}
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C {noconn.sym} 340 -220 0 0 {name=l1}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -30,6 +30,7 @@ end process;
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DATA_OUT <= D after delay;
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}
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K {}
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V {reg [width-1:0] D;
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always @(posedge CK or posedge RESET) begin
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@ -46,6 +47,7 @@ end
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assign #del DATA_OUT=D;
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}
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S {}
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F {}
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E {}
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C {opin.sym} 440 -230 0 0 {name=p3 lab=DATA_OUT[width-1:0] verilog_type=wire}
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C {ipin.sym} 280 -210 0 0 {name=p2 lab=CK}
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@ -60,3 +62,4 @@ C {use.sym} 360 -460 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;}
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C {noconn.sym} 440 -230 0 0 {name=l1}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.6RC file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -180,6 +180,7 @@ ADD=3;
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end
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}
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S {}
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F {}
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E {}
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T {Double edge triggered Flip FLop} 1090 -660 0 0 0.5 0.5 {}
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N 440 -350 470 -350 {lab=A}
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@ -197,8 +198,7 @@ N 810 -360 840 -360 {lab=A}
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N 920 -360 950 -360 {lab=Y_BUF}
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N 780 -90 810 -90 {lab=B}
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N 890 -90 920 -90 {lab=BN}
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N 1300 -430 1310 -430 {lab=#net1}
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N 1300 -570 1310 -570 {lab=#net2}
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N 1300 -570 1310 -570 {lab=#net1}
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N 1350 -550 1380 -550 {lab=AL1}
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N 1350 -610 1350 -550 {lab=AL1}
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N 1300 -610 1350 -610 {lab=AL1}
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@ -209,6 +209,9 @@ N 1080 -570 1170 -570 {lab=CK}
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N 1080 -610 1160 -610 {lab=A}
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N 1110 -470 1160 -470 {lab=A}
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N 1110 -610 1110 -470 {lab=A}
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N 1300 -430 1310 -430 {lab=#net2}
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N 990 -690 990 -670 {lab=DOUT[7:0]}
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N 940 -840 940 -820 {lab=DATA_OUT[7:0]}
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C {title.sym} 160 -30 0 0 {name=l2}
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C {nr2.sym} 510 -330 0 0 {name=x1 }
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C {lab_pin.sym} 440 -350 2 1 {name=p20 lab=A}
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@ -307,3 +310,15 @@ C {lab_pin.sym} 1230 -540 2 1 {name=p56 lab=RST verilog_type=reg}
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C {lab_pin.sym} 1230 -400 2 1 {name=p58 lab=RST verilog_type=reg}
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C {lab_pin.sym} 1350 -610 0 1 {name=p65 lab=AL1}
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C {lab_pin.sym} 1350 -470 0 1 {name=p66 lab=AL2}
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C {noconn.sym} 160 -430 1 0 {name=l1}
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C {noconn.sym} 160 -390 1 0 {name=l3}
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C {noconn.sym} 160 -350 1 0 {name=l4}
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C {noconn.sym} 160 -320 1 0 {name=l5}
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C {noconn.sym} 160 -300 1 0 {name=l6}
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C {noconn.sym} 160 -280 1 0 {name=l7}
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C {noconn.sym} 160 -260 1 0 {name=l8}
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C {noconn.sym} 160 -240 1 0 {name=l9}
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C {noconn.sym} 160 -220 1 0 {name=l10}
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C {noconn.sym} 160 -200 1 0 {name=l11}
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C {noconn.sym} 990 -670 0 0 {name=l12}
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C {noconn.sym} 940 -820 0 0 {name=l13}
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