diff --git a/src/spice.awk b/src/spice.awk
index 9b41eff1..fa33b2ca 100755
--- a/src/spice.awk
+++ b/src/spice.awk
@@ -211,13 +211,24 @@ function process(        i,j, iprefix, saveinstr, savetype, saveanalysis)
      sub(/^#/,"",iprefix)
      sub(/#.*/,"",iprefix)
      sub("#" iprefix "#", iprefix,$i)
-     gsub(/,/, "," iprefix,$i)
+     gsub(/,/, "," iprefix, $i)
      ## 20160301 add '?1' if missing in format string
      if(i>1 && ( $(i-1) !~/^\?/) )  {
        $i = "?1 " $i
      }
      $0 = $0  # reparse input line
    }
+   # prefix applied to symbol pin, like for example prepending negation operator '~' to pin: 
+   # format= ... #~#@@A[3:0] --> #~#?4 A[3],A[2],A[1],A[0] --> ~A[3],~A[2],~A[1],~A[0]
+   if($i ~/^#[~a-zA-Z_0-9]+#\?/) {
+     iprefix=$i
+     sub(/^#/,"",iprefix)
+     sub(/#.*/,"",iprefix)
+     sub("#" iprefix "#", "",$i)
+     $(i+1) = iprefix $(i+1)
+     gsub(/,/, "," iprefix, $(i+1))
+     $0 = $0  # reparse input line
+   }
  }
  ## 20140506 do not transform {} of variation groups
  ## nmos N {
@@ -274,76 +285,76 @@ function process(        i,j, iprefix, saveinstr, savetype, saveanalysis)
      }
    }
 
- #### this is never executed: commented lines are processed and skipped above
- # } else if( $1 ~ /^\*\.(ipin|opin|iopin)/ ) {
- #   num=split($2,name,",")
- #   for(i=1;i<=num;i++) print $1 " " name[i]
-
- } else if(  tolower($1) ~ /\.subckt/) {
-  # remove m=.. from subcircuit definition since m= is a multiplier not a param
-  sub(/ m=[0-9]+/," ",$0)
-  gsub(","," ",$0)
-  print $0
- } else {
-  # handle uncommon primitives that have a prefix before the device name
-  if(tolower($1) in special_devs) {
-    # YDELAY ?1 Rda[4],Rda[3],Rda[2],Rda[1],Rda[0] ?1 softrst[4],softrst[3],...
-    devprefix = $1
-    num = split($3, name, ",")
-    $1 = ""
-    for(i = 0; i < num; i++) {
-      if(i) $1 = $1 ","
-      $1 = $1 devprefix
-    }
-    num = split($1, name, ",")
-    $0 = $0
+  #### this is never executed: commented lines are processed and skipped above
+  # } else if( $1 ~ /^\*\.(ipin|opin|iopin)/ ) {
+  #   num=split($2,name,",")
+  #   for(i=1;i<=num;i++) print $1 " " name[i]
+ 
+  } else if(  tolower($1) ~ /\.subckt/) {
+   # remove m=.. from subcircuit definition since m= is a multiplier not a param
+   sub(/ m=[0-9]+/," ",$0)
+   gsub(","," ",$0)
+   print $0
   } else {
-    num = split($1, name, ",")
-  }
-  if(num==0) print ""
-
-
-  for(j=2;j<=NF;j+=1)  		# start from 2 not from 3 20070221
-  {
-    #       ............ --> matches ?n and ?-n
-    # some CDL netlists have this: $SUB=?1 B where B is a node
-    if($j ~/^(.*=)?\?-?[0-9]+$/) continue	# handle the case that $2 not pinlist  20070221
-    arg_num[j]=split($j,tmp,",")
-    for(k=1;k<=arg_num[j]; k++) {
-     arg_name[j,k]=tmp[k]
-    }
-  }
-  for(i=1;i<=num;i++)
-  {
-   printf "%s ", spiceprefix name[i]
-
-   for(j=2;j<=NF;j++)
-   {
-    #         ............ --> matches ?n and ?-n
-    # some CDL netlists have this: $SUB=?1 B where B is a node
-    if($j !~ /^(.*=)?\?-?[0-9]+$/)
-    {
-      printf "%s ", $j # if not a node just print it
-    }
-    else
-    {
-     nmult=$(j)
-     if(nmult ~ /^(.*=)/) { # some CDL netlists have this: $SUB=?1 B where B is a node
-       sub(/=.*/, "=", nmult)
-       printf "%s", nmult
+   # handle uncommon primitives that have a prefix before the device name
+   if(tolower($1) in special_devs) {
+     # YDELAY ?1 Rda[4],Rda[3],Rda[2],Rda[1],Rda[0] ?1 softrst[4],softrst[3],...
+     devprefix = $1
+     num = split($3, name, ",")
+     $1 = ""
+     for(i = 0; i < num; i++) {
+       if(i) $1 = $1 ","
+       $1 = $1 devprefix
      }
-     nmult=$(j++)
-     sub(/(.*=)?\?/,"",nmult)
-     if(nmult+0==-1) nmult=arg_num[j]
-     for(l=0;l<nmult+0;l++)
-     {
-      ii=(l+nmult*(i-1))%arg_num[j]+1
-      printf "%s ", arg_name[j,ii]
-     }
-    }
+     num = split($1, name, ",")
+     $0 = $0
+   } else {
+     num = split($1, name, ",")
+   }
+   if(num==0) print ""
+ 
+ 
+   for(j=2;j<=NF;j+=1)  		# start from 2 not from 3 20070221
+   {
+     #       ............ --> matches ?n and ?-n
+     # some CDL netlists have this: $SUB=?1 B where B is a node
+     if($j ~/^(.*=)?\?-?[0-9]+$/) continue	# handle the case that $2 not pinlist  20070221
+     arg_num[j]=split($j,tmp,",")
+     for(k=1;k<=arg_num[j]; k++) {
+      arg_name[j,k]=tmp[k]
+     }
+   }
+   for(i=1;i<=num;i++)
+   {
+    printf "%s ", spiceprefix name[i]
+ 
+    for(j=2;j<=NF;j++)
+    {
+     #         ............ --> matches ?n and ?-n
+     # some CDL netlists have this: $SUB=?1 B where B is a node
+     if($j !~ /^(.*=)?\?-?[0-9]+$/)
+     {
+       printf "%s ", $j # if not a node just print it
+     }
+     else
+     {
+      nmult=$(j)
+      if(nmult ~ /^(.*=)/) { # some CDL netlists have this: $SUB=?1 B where B is a node
+        sub(/=.*/, "=", nmult)
+        printf "%s", nmult
+      }
+      nmult=$(j++)
+      sub(/(.*=)?\?/,"",nmult)
+      if(nmult+0==-1) nmult=arg_num[j]
+      for(l=0;l<nmult+0;l++)
+      {
+       ii=(l+nmult*(i-1))%arg_num[j]+1
+       printf "%s ", arg_name[j,ii]
+      }
+     }
+    }
+    printf "\n"
    }
-   printf "\n"
   }
- }
 }
 
diff --git a/xschem_library/logic/bf.sch b/xschem_library/logic/bf.sch
index 719aadae..682d90f9 100644
--- a/xschem_library/logic/bf.sch
+++ b/xschem_library/logic/bf.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -21,9 +21,11 @@ v {xschem version=3.4.4 file_version=1.2
 }
 G {
 Y <= not (not A)  after delay ;}
+K {}
 V {assign #del Y=A;
 }
 S {}
+F {}
 E {}
 C {opin.sym} 670 -290 0 0 {name=p0 lab=Y}
 C {ipin.sym} 250 -290 0 0 {name=p3 lab=A}
@@ -37,3 +39,5 @@ library ieee;
 --         use SYNOPSYS.ATTRIBUTES.ALL;
 }
 C {title.sym} 160 -30 0 0 {name=l2}
+C {noconn.sym} 670 -290 0 0 {name=l1}
+C {noconn.sym} 250 -290 0 1 {name=l3}
diff --git a/xschem_library/logic/eo.sch b/xschem_library/logic/eo.sch
index b8c9cd66..7b8fd3e7 100644
--- a/xschem_library/logic/eo.sch
+++ b/xschem_library/logic/eo.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -21,9 +21,11 @@ v {xschem version=3.4.4 file_version=1.2
 }
 G {
 Y <=  A xor B after delay ;}
+K {}
 V {
 assign #del Y=A^B;}
 S {}
+F {}
 E {}
 C {ipin.sym} 150 -320 0 0 {name=p2 lab=A}
 C {ipin.sym} 150 -350 0 0 {name=p3 lab=B}
@@ -38,3 +40,6 @@ library ieee;
 --         use SYNOPSYS.ATTRIBUTES.ALL;
 }
 C {title.sym} 160 -30 0 0 {name=l2}
+C {noconn.sym} 920 -350 0 0 {name=l1}
+C {noconn.sym} 150 -350 0 1 {name=l3}
+C {noconn.sym} 150 -320 0 1 {name=l4}
diff --git a/xschem_library/logic/ff.sch b/xschem_library/logic/ff.sch
index 341e03e6..2e2c9fa1 100644
--- a/xschem_library/logic/ff.sch
+++ b/xschem_library/logic/ff.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -30,6 +30,7 @@ end if ;
 end process ;
 
  }
+K {}
 V {reg iQ;
 always @(posedge CK or posedge RST) begin
   if(RST)    iQ=0;
@@ -39,6 +40,7 @@ end
 assign #del Q=iQ;
 }
 S {}
+F {}
 E {}
 C {ipin.sym} 60 -150 0 0 {name=p1 lab=D}
 C {opin.sym} 130 -130 0 0 {name=p2 verilog_type=wire lab=Q}
@@ -49,3 +51,7 @@ C {use.sym} 100 -440 0 0 {------------------------------------------------
 library ieee;
         use ieee.std_logic_1164.all;
         use ieee.numeric_std.all;}
+C {noconn.sym} 130 -130 0 0 {name=l1}
+C {noconn.sym} 60 -150 0 1 {name=l3}
+C {noconn.sym} 60 -130 0 1 {name=l4}
+C {noconn.sym} 60 -110 0 1 {name=l5}
diff --git a/xschem_library/logic/ff.sym b/xschem_library/logic/ff.sym
index 287a0754..cf03099c 100644
--- a/xschem_library/logic/ff.sym
+++ b/xschem_library/logic/ff.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 }
-G {type=subcircuit
+G {}
+K {type=subcircuit
 vhdl_stop=true 
 verilog_stop=true
 format="@name @pinlist @symname" 
@@ -27,6 +28,7 @@ template="name=x1 delay=\\"400 ps\\" del=400"
 generic_type="delay=time"}
 V {}
 S {}
+F {}
 E {}
 L 4 -50 -30 50 -30 {}
 L 4 -50 30 50 30 {}
diff --git a/xschem_library/logic/ram.sch b/xschem_library/logic/ram.sch
index 66939572..873196ab 100644
--- a/xschem_library/logic/ram.sch
+++ b/xschem_library/logic/ram.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -93,6 +93,7 @@ assign #oe_delay DOUT = OEN ? 'bz: iidata;
 
 }
 S {}
+F {}
 E {}
 L 4 290 -560 290 -260 {}
 L 4 210 -560 210 -260 {}
@@ -180,3 +181,4 @@ C {arch_declarations.sym} 750 -630 0 0 {    constant RAM_DEPTH :integer := 2**di
     signal mem : RAMARR (0 to RAM_DEPTH-1);
     signal data : std_logic_vector(width-1 downto 0);
 }
+C {noconn.sym} 340 -220 0 0 {name=l1}
diff --git a/xschem_library/logic/sync_reg.sch b/xschem_library/logic/sync_reg.sch
index 02491629..17d2f780 100644
--- a/xschem_library/logic/sync_reg.sch
+++ b/xschem_library/logic/sync_reg.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -30,6 +30,7 @@ end process;
 
 DATA_OUT <= D after delay;
 }
+K {}
 V {reg [width-1:0] D;
 
 always @(posedge CK or posedge RESET) begin
@@ -46,6 +47,7 @@ end
 assign #del DATA_OUT=D;
 }
 S {}
+F {}
 E {}
 C {opin.sym} 440 -230 0 0 {name=p3 lab=DATA_OUT[width-1:0] verilog_type=wire}
 C {ipin.sym} 280 -210 0 0 {name=p2 lab=CK}
@@ -60,3 +62,4 @@ C {use.sym} 360 -460 0 0 {------------------------------------------------
 library ieee;
         use ieee.std_logic_1164.all;
         use ieee.numeric_std.all;}
+C {noconn.sym} 440 -230 0 0 {name=l1}
diff --git a/xschem_library/logic/testbench.sch b/xschem_library/logic/testbench.sch
index 3b7d7982..71fe437e 100644
--- a/xschem_library/logic/testbench.sch
+++ b/xschem_library/logic/testbench.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.6RC file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -180,6 +180,7 @@ ADD=3;
 end
 }
 S {}
+F {}
 E {}
 T {Double edge triggered Flip FLop} 1090 -660 0 0 0.5 0.5 {}
 N 440 -350 470 -350 {lab=A}
@@ -197,8 +198,7 @@ N 810 -360 840 -360 {lab=A}
 N 920 -360 950 -360 {lab=Y_BUF}
 N 780 -90 810 -90 {lab=B}
 N 890 -90 920 -90 {lab=BN}
-N 1300 -430 1310 -430 {lab=#net1}
-N 1300 -570 1310 -570 {lab=#net2}
+N 1300 -570 1310 -570 {lab=#net1}
 N 1350 -550 1380 -550 {lab=AL1}
 N 1350 -610 1350 -550 {lab=AL1}
 N 1300 -610 1350 -610 {lab=AL1}
@@ -209,6 +209,9 @@ N 1080 -570 1170 -570 {lab=CK}
 N 1080 -610 1160 -610 {lab=A}
 N 1110 -470 1160 -470 {lab=A}
 N 1110 -610 1110 -470 {lab=A}
+N 1300 -430 1310 -430 {lab=#net2}
+N 990 -690 990 -670 {lab=DOUT[7:0]}
+N 940 -840 940 -820 {lab=DATA_OUT[7:0]}
 C {title.sym} 160 -30 0 0 {name=l2}
 C {nr2.sym} 510 -330 0 0 {name=x1 }
 C {lab_pin.sym} 440 -350 2 1 {name=p20 lab=A}
@@ -307,3 +310,15 @@ C {lab_pin.sym} 1230 -540 2 1 {name=p56 lab=RST verilog_type=reg}
 C {lab_pin.sym} 1230 -400 2 1 {name=p58 lab=RST verilog_type=reg}
 C {lab_pin.sym} 1350 -610 0 1 {name=p65 lab=AL1}
 C {lab_pin.sym} 1350 -470 0 1 {name=p66 lab=AL2}
+C {noconn.sym} 160 -430 1 0 {name=l1}
+C {noconn.sym} 160 -390 1 0 {name=l3}
+C {noconn.sym} 160 -350 1 0 {name=l4}
+C {noconn.sym} 160 -320 1 0 {name=l5}
+C {noconn.sym} 160 -300 1 0 {name=l6}
+C {noconn.sym} 160 -280 1 0 {name=l7}
+C {noconn.sym} 160 -260 1 0 {name=l8}
+C {noconn.sym} 160 -240 1 0 {name=l9}
+C {noconn.sym} 160 -220 1 0 {name=l10}
+C {noconn.sym} 160 -200 1 0 {name=l11}
+C {noconn.sym} 990 -670 0 0 {name=l12}
+C {noconn.sym} 940 -820 0 0 {name=l13}