From 4beb2d08a649ebddf9c833a8ff82b1df60af4ee7 Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Tue, 24 Oct 2023 00:07:36 +0200 Subject: [PATCH] update example schematics --- tests/xschemtest.tcl | 4 ++-- xschem_library/examples/LCC_instances.sch | 1 + xschem_library/examples/plot_manipulation.sch | 7 ++++--- xschem_library/examples/tesla.sch | 11 ++++++----- xschem_library/examples/test_bus_tap.sch | 4 ++-- xschem_library/ngspice/delta_sigma.sch | 1 + xschem_library/rom8k/rom8k.sch | 1 + 7 files changed, 17 insertions(+), 12 deletions(-) diff --git a/tests/xschemtest.tcl b/tests/xschemtest.tcl index 0c5d65eb..2c2d633c 100644 --- a/tests/xschemtest.tcl +++ b/tests/xschemtest.tcl @@ -190,13 +190,13 @@ proc test_xschem_simulation {{f simulate_ff.sch}} { proc netlist_test {} { global netlist_dir foreach {f t h} { - rom8k.sch spice 1998661799 + rom8k.sch spice 1947979332 greycnt.sch verilog 2899796185 autozero_comp.sch spice 751826850 loading.sch vhdl 2975204502 mos_power_ampli.sch spice 1986885043 hierarchical_tedax.sch tedax 998070173 - LCC_instances.sch spice 268038818 + LCC_instances.sch spice 1619668159 pcb_test1.sch tedax 1925087189 test_doublepin.sch spice 894741562 simulate_ff.sch spice 574849766 diff --git a/xschem_library/examples/LCC_instances.sch b/xschem_library/examples/LCC_instances.sch index 00e14a96..78f3297a 100644 --- a/xschem_library/examples/LCC_instances.sch +++ b/xschem_library/examples/LCC_instances.sch @@ -118,6 +118,7 @@ write LCC_instances.raw set appendwrite dc v1 3 0 -0.001 write LCC_instances.raw +quit 0 .endc "} C {code.sym} 840 -190 0 0 {name=MODEL diff --git a/xschem_library/examples/plot_manipulation.sch b/xschem_library/examples/plot_manipulation.sch index 5cfa6558..09c82e57 100644 --- a/xschem_library/examples/plot_manipulation.sch +++ b/xschem_library/examples/plot_manipulation.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -108,7 +108,8 @@ C {lab_pin.sym} 630 -280 0 1 {name=p10 lab=MINUS net_name=true} C {lab_pin.sym} 830 -360 0 1 {name=p11 lab=DIFFOUT net_name=true} C {lab_pin.sym} 240 -230 0 0 {name=p13 lab=GN net_name=true} C {lab_pin.sym} 30 -280 0 0 {name=p14 lab=0 net_name=true} -C {vsource.sym} 30 -310 0 0 {name=VPLUS value="2.5 pwl 0 2.4 10n 2.4 10.1n 2.6" net_name=true} +C {vsource.sym} 30 -310 0 0 {name=VPLUS value=2.5 net_name=true +} C {lab_pin.sym} 60 -370 0 1 {name=p15 lab=PLUS net_name=true} C {lab_pin.sym} 30 -430 0 0 {name=p16 lab=0 net_name=true} C {vsource.sym} 30 -460 0 0 {name=V1 value=2.5 net_name=true} @@ -159,7 +160,7 @@ setscale vcc $ set as xaxis for myplot settype voltage vcc write plot_manipulation.raw plot s_vec - +quit 0 .endc ** ngspice diff --git a/xschem_library/examples/tesla.sch b/xschem_library/examples/tesla.sch index 83d2e276..a37d9c38 100644 --- a/xschem_library/examples/tesla.sch +++ b/xschem_library/examples/tesla.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -32,8 +32,8 @@ ypos2=2 divy=5 subdivy=1 unity=k -x1=4e-10 -x2=0.001 +x1=0.000952652 +x2=0.000957538 divx=5 subdivx=1 node=hv @@ -49,8 +49,8 @@ ypos2=2 divy=5 subdivy=1 unity=1 -x1=4e-10 -x2=0.001 +x1=0.000952652 +x2=0.000957538 divx=5 subdivx=1 @@ -174,6 +174,7 @@ tran 40n 1m uic meas tran iavg AVG i(vvcc) from=950u to=990u save tran p(q5) i(l1) i(l2) write tesla.raw +quit 0 .endc "} C {lab_pin.sym} 140 -680 0 0 {name=p1 lab=VCC} diff --git a/xschem_library/examples/test_bus_tap.sch b/xschem_library/examples/test_bus_tap.sch index f0ac5861..fd2f75be 100644 --- a/xschem_library/examples/test_bus_tap.sch +++ b/xschem_library/examples/test_bus_tap.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -27,7 +27,7 @@ E {} P 4 7 630 -290 630 -320 620 -320 630 -347.5 640 -320 630 -320 630 -290 {fill=true} T {Specifying @lab will result in net -@#1:net_name} 640 -310 0 0 0.4 0.4 {name=l6 layer=4} +@#0:net_name} 640 -310 0 0 0.4 0.4 {name=l6 layer=4} T {Title symbol has embedded TCL command to enable show_pin_net_names } 180 -110 0 0 0.4 0.4 { layer=7} T {@#1:net_name} 1120 -1030 0 0 0.4 0.4 {name=l19 layer=4} diff --git a/xschem_library/ngspice/delta_sigma.sch b/xschem_library/ngspice/delta_sigma.sch index 0aa3dfdd..ffd97dcf 100644 --- a/xschem_library/ngspice/delta_sigma.sch +++ b/xschem_library/ngspice/delta_sigma.sch @@ -114,6 +114,7 @@ value=" * save all tran 0.2n 9u uic write delta_sigma.raw + quit 0 .endc "} C {vsource.sym} 270 -540 0 1 {name=v3 diff --git a/xschem_library/rom8k/rom8k.sch b/xschem_library/rom8k/rom8k.sch index c5ab19ab..392a0484 100644 --- a/xschem_library/rom8k/rom8k.sch +++ b/xschem_library/rom8k/rom8k.sch @@ -388,6 +388,7 @@ vvss vss 0 0 tran 0.2n 480n uic write rom8k_ngspice.raw acct + quit 0 .endc ** download models from here: