add command "xschem attach_labels 2" to attach lab_show.sym on selected component with unconnected pins, add command "xschem show_unconnected_pins" to add to all instances, added also in Highlight menu
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@ -585,8 +585,10 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
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<li><kbd> arc</kbd></li><pre>
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Start a GUI placement of an arc.
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User should click 3 unaligned points to define the arc </pre>
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<li><kbd> attach_labels</kbd></li><pre>
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Attach net labels to selected component(s) instance(s) </pre>
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<li><kbd> attach_labels [interactive]</kbd></li><pre>
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Attach net labels to selected component(s) instance(s)
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Optional integer 'interactive' (default: 0) is passed to attach_labels_to_inst().
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setting interactive=2 will place lab_show.sym labels on unconnected instance pins </pre>
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<li><kbd> bbox begin|end</kbd></li><pre>
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Start/end bounding box calculation: parameter is either 'begin' or 'end' </pre>
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<li><kbd> break_wires [remove]</kbd></li><pre>
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@ -1562,6 +1564,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
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If 'val' not given (no attribute value) delete attribute from text
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If '-fast' argument is given does not redraw and is not undoable
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If '-fastundo' is given same as above but action is undoable.</pre>
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<li><kbd> show_unconnected_pins</kbd></li><pre>
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Add a "lab_show.sym" to all instance pins that are not connected to anything </pre>
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<li><kbd> simulate [callback]</kbd></li><pre>
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Run a simulation (start simulator configured as default in
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Tools -> Configure simulators and tools)
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@ -1779,6 +1783,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
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</ul>
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@ -1282,7 +1282,10 @@ int unselect_partial_sel_wires(void)
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}
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/* interactive = 0: do not present dialog box
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* interactive = 1: present dialog box
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* interactive = 2: attach lab_show to unconnected pins, no dialog box
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*/
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void attach_labels_to_inst(int interactive) /* offloaded from callback.c 20171005 */
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{
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xSymbol *symbol;
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@ -1294,6 +1297,7 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
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char *prop=NULL; /* 20161122 overflow safe */
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char *symname_pin = NULL;
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char *symname_wire = NULL;
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char *symname_show = NULL;
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char *type=NULL;
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short dir;
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int k,ii, skip;
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@ -1310,7 +1314,8 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
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my_strdup(_ALLOC_ID_, &symname_pin, tcleval("find_file_first lab_pin.sym"));
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my_strdup(_ALLOC_ID_, &symname_wire, tcleval("find_file_first lab_wire.sym"));
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if(symname_pin && symname_wire) {
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my_strdup(_ALLOC_ID_, &symname_show, tcleval("find_file_first lab_show.sym"));
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if(symname_pin && symname_wire && symname_show) {
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rebuild_selected_array();
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k = xctx->lastsel;
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first_call=1;
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@ -1321,7 +1326,7 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
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my_strcat(_ALLOC_ID_, &prop, "_");
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tclsetvar("custom_label_prefix",prop);
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if(interactive && !do_all_inst) {
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if(interactive == 1 && !do_all_inst) {
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dbg(1,"attach_labels_to_inst(): invoking tcl attach_labels_to_inst\n");
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tcleval("attach_labels_to_inst");
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if(!strcmp(tclgetvar("tctx::rcode"),"") ) {
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@ -1330,7 +1335,7 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
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return;
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}
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}
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if(interactive == 0 ) {
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if(interactive != 1 ) {
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tclsetvar("tctx::rcode", "yes");
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tclsetvar("use_lab_wire", "0");
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tclsetvar("use_label_prefix", "0");
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@ -1418,7 +1423,9 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
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} else {
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rot1=(short)((rot+rotated_text)%4); /* 20111103 20171208 text_rotation */
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}
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if(!tclgetboolvar("use_lab_wire")) {
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if(interactive == 2) {
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place_symbol(-1,symname_show, pinx0, piny0, rot1, dir, prop, 2, first_call, 1/*to_push_undo*/);
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} else if(!tclgetboolvar("use_lab_wire")) {
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place_symbol(-1,symname_pin, pinx0, piny0, rot1, dir, prop, 2, first_call, 1/*to_push_undo*/);
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} else {
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place_symbol(-1,symname_wire, pinx0, piny0, rot1, dir, prop, 2, first_call, 1/*to_push_undo*/);
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@ -1443,8 +1450,14 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
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fprintf(errfp, "attach_labels_to_inst(): location of schematic labels not found\n");
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tcleval("alert_ {attach_labels_to_inst(): location of schematic labels not found} {}");
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}
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/* if hilights are present in schematic propagate to new added labels */
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if(xctx->hilight_nets) {
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propagate_hilights(1, 0, XINSERT_NOREPLACE);
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redraw_hilights(0);
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}
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my_free(_ALLOC_ID_, &symname_pin);
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my_free(_ALLOC_ID_, &symname_wire);
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my_free(_ALLOC_ID_, &symname_show);
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}
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void delete_files(void)
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@ -1539,6 +1539,19 @@ static int reset_node_data_and_rehash()
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return err;
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}
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/* add lab_show.sym to instance pins that are not connected to wires / labels / other instances */
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void show_unconnected_pins(void)
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{
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int i;
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for(i = 0; i < xctx->instances; ++i)
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{
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select_element(i, SELECTED, 1, 0);
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}
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rebuild_selected_array();
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attach_labels_to_inst(2);
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unselect_all(1);
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}
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int prepare_netlist_structs(int for_netl)
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{
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int err = 0;
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@ -377,12 +377,17 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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xctx->ui_state2 = MENUSTARTARC;
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}
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/* attach_labels
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* Attach net labels to selected component(s) instance(s) */
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/* attach_labels [interactive]
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* Attach net labels to selected component(s) instance(s)
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* Optional integer 'interactive' (default: 0) is passed to attach_labels_to_inst().
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* setting interactive=2 will place lab_show.sym labels on unconnected instance pins */
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else if(!strcmp(argv[1], "attach_labels"))
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{
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int interactive = 0;
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if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
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attach_labels_to_inst(0);
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if(argc > 2) interactive = atoi(argv[2]);
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attach_labels_to_inst(interactive);
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Tcl_ResetResult(interp);
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}
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else { cmd_found = 0;}
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@ -5828,6 +5833,14 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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Tcl_ResetResult(interp);
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}
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}
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/* show_unconnected_pins
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* Add a "lab_show.sym" to all instance pins that are not connected to anything */
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else if(!strcmp(argv[1], "show_unconnected_pins") )
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{
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if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
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show_unconnected_pins();
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Tcl_ResetResult(interp);
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}
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/* simulate [callback]
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* Run a simulation (start simulator configured as default in
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* Tools -> Configure simulators and tools)
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@ -1753,6 +1753,7 @@ extern void copy_hilights(void);
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extern void display_hilights(int what, char **str);
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extern void redraw_hilights(int clear);
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extern void set_tcl_netlist_type(void);
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extern void show_unconnected_pins(void);
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extern int prepare_netlist_structs(int for_netlist);
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extern int skip_instance(int i, int skip_short, int lvs_ignore);
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extern int shorted_instance(int i, int lvs_ignore);
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@ -9387,6 +9387,8 @@ proc build_widgets { {topwin {} } } {
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$topwin.menubar.hilight add command -label {Un-highlight selected net/pins} \
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-command "xschem unhilight" -accelerator Ctrl+K
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# 20160413
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$topwin.menubar.hilight add command -label {Show labels on unconnected instance pins} \
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-command "xschem show_unconnected_pins"
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$topwin.menubar.hilight add checkbutton \
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-selectcolor $selectcolor -label {Auto-highlight net/pins} -variable auto_hilight
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$topwin.menubar.hilight add checkbutton -label {Enable highlight connected instances} \
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@ -27,6 +27,6 @@ V {}
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S {}
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F {}
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E {}
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L 4 -20 -20 0 0 {}
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L 4 -20 -10 0 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=none}
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T {@#0:net_name} -22.5 -30.625 0 1 0.33 0.33 {}
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T {@#0:net_name} -22.5 -20.625 0 1 0.33 0.33 {}
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