lab_show.sym: set pin dir to "none" so will not act as a signal driver or as a driven instance
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -25,7 +25,8 @@ template="name=l1"
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highlight=true}
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V {}
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S {}
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F {}
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E {}
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L 4 -20 -20 0 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=none}
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T {@#0:net_name} -22.5 -30.625 0 1 0.33 0.33 {}
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