removed logicx() obsoleted function
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9b4534d6b0
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40eaefbb82
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@ -943,27 +943,6 @@ int eval_logic_expr(int inst, int output)
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return stack[0];
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}
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void logicx()
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{
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int i, rects, j;
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static int map[] = {LOGIC_0, LOGIC_1, LOGIC_X};
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free_hilight_hash();
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prepare_netlist_structs(0);
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for(i=0;i<xctx->instances;i++) {
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rects = (xctx->inst[i].ptr+ xctx->sym)->rects[PINLAYER];
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for(j=0;j<rects;j++) {
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if( xctx->inst[i].node && xctx->inst[i].node[j]) {
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bus_hilight_lookup(xctx->inst[i].node[j], map[2], XINSERT_NOREPLACE);
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}
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}
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}
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for(i=0;i<xctx->wires;i++) {
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bus_hilight_lookup(xctx->wire[i].node, 0, XINSERT_NOREPLACE);
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}
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propagate_hilights(1, 0, XINSERT_NOREPLACE);
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draw();
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}
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void propagate_logic()
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{
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char *propagated_net=NULL;
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@ -1431,12 +1431,6 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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if(argc > 2) logic_set(atoi(argv[2]));
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Tcl_ResetResult(interp);
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}
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else if(!strcmp(argv[1],"logicx"))
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{
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cmd_found = 1;
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logicx();
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Tcl_ResetResult(interp);
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}
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}
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else if(argv[1][0] == 'm') {
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@ -1106,7 +1106,6 @@ extern void print_generic(FILE *fd, char *ent_or_comp, int symbol);
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extern void print_verilog_param(FILE *fd, int symbol);
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extern void hilight_net(int to_waveform);
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extern void logic_set(int v);
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extern void logicx();
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extern int hilight_netname(const char *name);
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extern void unhilight_net();
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extern void propagate_hilights(int set, int clear, int mode);
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@ -527,6 +527,7 @@ N 6410 -620 6490 -620 { lab=S3}
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N 6410 -700 6430 -700 { lab=#net51}
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N 6410 -450 6490 -450 { lab=S2}
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N 6250 -110 6290 -110 { lab=VSS}
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N 5740 -300 5820 -300 { lab=Q_FF}
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C {nand2_1.sym} 420 -2020 0 0 {name=x45 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
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C {nand2_1.sym} 650 -1760 0 0 {name=x49 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
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C {nand3_1.sym} 420 -1870 0 0 {name=x51 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
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@ -652,3 +653,8 @@ C {lab_pin.sym} 6490 -450 0 1 {name=l20 sig_type=std_logic lab=S2}
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C {lab_pin.sym} 6490 -280 0 1 {name=l21 sig_type=std_logic lab=S1}
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C {lab_pin.sym} 6490 -110 0 1 {name=l22 sig_type=std_logic lab=S0}
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C {lab_pin.sym} 6250 -110 0 0 {name=l23 sig_type=std_logic lab=VSS}
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C {lab_pin.sym} 5560 -260 0 0 {name=l1 sig_type=std_logic lab=CLEAR_}
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C {lab_pin.sym} 5560 -300 0 0 {name=l24 sig_type=std_logic lab=CLK}
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C {lab_pin.sym} 5820 -300 0 1 {name=l27 sig_type=std_logic lab=Q_FF}
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C {dfrtp_1.sym} 5650 -280 0 0 {name=x2 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
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C {lab_pin.sym} 5560 -280 0 0 {name=l26 sig_type=std_logic lab=DATA}
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