diff --git a/src/hilight.c b/src/hilight.c
index 638aa138..ed3043a0 100644
--- a/src/hilight.c
+++ b/src/hilight.c
@@ -943,27 +943,6 @@ int eval_logic_expr(int inst, int output)
   return stack[0];
 }
 
-void logicx()
-{
-  int i, rects, j;
-  static int map[] = {LOGIC_0, LOGIC_1, LOGIC_X};
-  free_hilight_hash();
-  prepare_netlist_structs(0);
-  for(i=0;i<xctx->instances;i++) {
-    rects = (xctx->inst[i].ptr+ xctx->sym)->rects[PINLAYER];
-    for(j=0;j<rects;j++) {
-      if( xctx->inst[i].node && xctx->inst[i].node[j]) {
-         bus_hilight_lookup(xctx->inst[i].node[j], map[2], XINSERT_NOREPLACE);
-      }
-    }
-  }
-  for(i=0;i<xctx->wires;i++) {
-    bus_hilight_lookup(xctx->wire[i].node, 0, XINSERT_NOREPLACE);
-  }
-  propagate_hilights(1, 0, XINSERT_NOREPLACE);
-  draw();
-}
-
 void propagate_logic()
 {
   char *propagated_net=NULL;
diff --git a/src/scheduler.c b/src/scheduler.c
index 22d6fc7c..913537fc 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -1431,12 +1431,6 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
       if(argc > 2) logic_set(atoi(argv[2]));
       Tcl_ResetResult(interp);
     }
-    else if(!strcmp(argv[1],"logicx"))
-    {
-      cmd_found = 1;
-      logicx();
-      Tcl_ResetResult(interp);
-    }
   }
 
   else if(argv[1][0] == 'm') {   
diff --git a/src/xschem.h b/src/xschem.h
index d577c3ef..842f5454 100644
--- a/src/xschem.h
+++ b/src/xschem.h
@@ -1106,7 +1106,6 @@ extern void print_generic(FILE *fd, char *ent_or_comp, int symbol);
 extern void print_verilog_param(FILE *fd, int symbol);
 extern void hilight_net(int to_waveform);
 extern void logic_set(int v);
-extern void logicx();
 extern int hilight_netname(const char *name);
 extern void unhilight_net();
 extern void propagate_hilights(int set, int clear, int mode);
diff --git a/xschem_library/xschem_simulator/logic_test.sch b/xschem_library/xschem_simulator/logic_test.sch
index 2434041c..71aa8073 100644
--- a/xschem_library/xschem_simulator/logic_test.sch
+++ b/xschem_library/xschem_simulator/logic_test.sch
@@ -527,6 +527,7 @@ N 6410 -620 6490 -620 { lab=S3}
 N 6410 -700 6430 -700 { lab=#net51}
 N 6410 -450 6490 -450 { lab=S2}
 N 6250 -110 6290 -110 { lab=VSS}
+N 5740 -300 5820 -300 { lab=Q_FF}
 C {nand2_1.sym} 420 -2020 0 0 {name=x45 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
 C {nand2_1.sym} 650 -1760 0 0 {name=x49 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
 C {nand3_1.sym} 420 -1870 0 0 {name=x51 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
@@ -652,3 +653,8 @@ C {lab_pin.sym} 6490 -450 0 1 {name=l20 sig_type=std_logic lab=S2}
 C {lab_pin.sym} 6490 -280 0 1 {name=l21 sig_type=std_logic lab=S1}
 C {lab_pin.sym} 6490 -110 0 1 {name=l22 sig_type=std_logic lab=S0}
 C {lab_pin.sym} 6250 -110 0 0 {name=l23 sig_type=std_logic lab=VSS}
+C {lab_pin.sym} 5560 -260 0 0 {name=l1 sig_type=std_logic lab=CLEAR_}
+C {lab_pin.sym} 5560 -300 0 0 {name=l24 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} 5820 -300 0 1 {name=l27 sig_type=std_logic lab=Q_FF}
+C {dfrtp_1.sym} 5650 -280 0 0 {name=x2 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
+C {lab_pin.sym} 5560 -280 0 0 {name=l26 sig_type=std_logic lab=DATA}