update inst_sch_select.sch, fix constrained move reset in intuitive_interface
This commit is contained in:
stefan schippers
parent
93722e8a21
commit
336a132219
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@ -1689,6 +1689,8 @@ static void end_shape_point_edit()
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int n = xctx->sel_array[0].n;
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int c = xctx->sel_array[0].col;
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move_objects(END,0,0,0);
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xctx->constr_mv=0;
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tcleval("set constr_mv 0" );
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xctx->poly[c][n].sel = SELECTED;
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xctx->shape_point_selected = 0;
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for(k=0; k<xctx->poly[c][n].points; ++k) {
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@ -1700,6 +1702,8 @@ static void end_shape_point_edit()
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int n = xctx->sel_array[0].n;
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int c = xctx->sel_array[0].col;
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move_objects(END,0,0,0);
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xctx->constr_mv=0;
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tcleval("set constr_mv 0" );
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xctx->rect[c][n].sel = SELECTED;
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xctx->shape_point_selected = 0;
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xctx->need_reb_sel_arr=1;
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@ -1708,6 +1712,8 @@ static void end_shape_point_edit()
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int n = xctx->sel_array[0].n;
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int c = xctx->sel_array[0].col;
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move_objects(END,0,0,0);
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xctx->constr_mv=0;
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tcleval("set constr_mv 0" );
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xctx->line[c][n].sel = SELECTED;
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xctx->shape_point_selected = 0;
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xctx->need_reb_sel_arr=1;
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@ -1715,6 +1721,8 @@ static void end_shape_point_edit()
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else if(xctx->lastsel == 1 && xctx->sel_array[0].type==WIRE) {
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int n = xctx->sel_array[0].n;
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move_objects(END,0,0,0);
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xctx->constr_mv=0;
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tcleval("set constr_mv 0" );
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xctx->wire[n].sel = SELECTED;
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xctx->shape_point_selected = 0;
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xctx->need_reb_sel_arr=1;
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@ -3556,15 +3564,17 @@ int rstate; /* (reduced state, without ShiftMask) */
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waves_callback(event, mx, my, key, button, aux, state);
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break;
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}
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/* end intuitive_interface copy or move */
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if(xctx->ui_state & STARTCOPY && xctx->drag_elements) {
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copy_objects(END);
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xctx->constr_mv=0;
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tcleval("set constr_mv 0" );
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xctx->drag_elements = 0;
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}
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else if(xctx->ui_state & STARTMOVE && xctx->drag_elements) {
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move_objects(END,0,0,0);
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xctx->constr_mv=0;
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tcleval("set constr_mv 0" );
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xctx->drag_elements = 0;
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}
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@ -1,6 +1,27 @@
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* comp3_read.cir
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.subckt comp3_read PLUS OUT MINUS
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v1 x 0 1.1
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e1 out x plus minus 0.5
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.subckt comp3_read MINUS OUT PLUS
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** parasitic netlist
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cparax1 net1 0 150f
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cparax2 net2 0 150f
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cparax3 net3 0 150f
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cparax4 net4 0 150f
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cparax5 net5 0 150f
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cparaxout out 0 180f
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M1 net1 GN1 0 0 nmos w=4u l=0.4u m=1
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M2 GN1 GN1 0 0 nmos w=4u l=0.4u m=1
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I0 VCC GN1 30u
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M3 net2 MINUS net1 0 nmos w=1.5u l=0.2u m=1
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M4 net3 PLUS net1 0 nmos w=1.5u l=0.2u m=1
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M5 net2 net2 VCC VCC pmos w=6u l=0.3u m=1
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M6 net3 net2 VCC VCC pmos w=6u l=0.3u m=1
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M14 net4 net3 VCC VCC pmos w=6u l=0.3u m=1
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.save v(gn1)
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.save v(net2)
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M7 net4 GN1 0 0 nmos w=4u l=0.4u m=1
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M8 net5 net4 0 0 nmos w=1u l=0.4u m=1
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M9 net5 net4 VCC VCC pmos w=2u l=0.4u m=1
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M10 OUT net5 0 0 nmos w=1u l=0.4u m=1
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M11 OUT net5 VCC VCC pmos w=2u l=0.4u m=1
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M13 net4 net4 net5 0 nmos w=2u l=0.1u m=1
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M12 net5 net5 net4 0 nmos w=2u l=0.1u m=1
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C2 GN1 0 200f m=1
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.ends
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@ -23,7 +23,9 @@ G {}
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K {type=subcircuit
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format="@name @pinlist @symname"
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template="name=x1"
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spice_sym_def="tcleval([read_data_nonewline [abs_sym_path comp3_read.cir]])"}
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xspice_sym_def="tcleval([read_data_nonewline [abs_sym_path comp3_read.cir]])"
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spice_sym_def="tcleval(.include [abs_sym_path comp3_read.cir])"}
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V {}
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S {}
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E {}
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@ -24,16 +24,16 @@ K {}
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V {}
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S {}
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E {}
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B 2 710 -620 1510 -220 {flags=graph
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y1=-0.013
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B 2 1240 -590 2040 -80 {flags=graph
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y1=0
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y2=2.1
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=-2.5e-09
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x2=4.75e-08
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x1=0
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x2=5e-08
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divx=5
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subdivx=1
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node="out1
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@ -49,16 +49,16 @@ unitx=1
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logx=0
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logy=0
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hilight_wave=-1}
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B 2 710 -940 1510 -620 {flags=graph
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y1=-0.013
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y2=2.1
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B 2 1240 -1010 2040 -600 {flags=graph
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y1=0
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y2=2
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=-2.5e-09
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x2=4.75e-08
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x1=0
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x2=5e-08
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divx=5
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subdivx=1
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@ -71,38 +71,48 @@ hilight_wave=-1
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color="4 7"
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node="plus minus"}
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T {Default instance:
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Uses comp3.sch} 10 -1190 0 0 0.4 0.4 { layer=7}
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Uses comp3.sch} 320 -950 0 0 0.4 0.4 { layer=7}
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T {Alternate instance:
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Uses comp3_parax.sch} 10 -980 0 0 0.4 0.4 { layer=8}
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Uses comp3_parax.sch} 10 -960 0 0 0.4 0.4 { layer=8}
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T {Alternate instance:
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Uses comp3_pex
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contained in attribute
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spice_sym_def
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No schematic used} 10 -780 0 0 0.4 0.4 { layer=9}
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No schematic used} 10 -760 0 0 0.4 0.4 { layer=9}
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T {Alternate instance:
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Uses comp3_empty.sch
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netlist embedded in global
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spice schematic attribute} 340 -920 0 0 0.4 0.4 { layer=11}
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spice schematic attribute} 320 -750 0 0 0.4 0.4 { layer=11}
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T {Alternate instance:
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Uses spice_sym_def to read in
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file comp3_file.cir
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no schematic used} 340 -620 0 0 0.4 0.4 { layer=12}
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no schematic used} 330 -450 0 0 0.4 0.4 { layer=12}
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T {The same symbol is simulated with 5 different implementations
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using instance 'schematic' and 'spice_sym_def' attributes} 510 -1050 0 0 0.6 0.6 { layer=4 slant=oblique}
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T {Instance based implementation selection.} 570 -1110 0 0 0.8 0.8 {}
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using instance 'schematic' and 'spice_sym_def ' attributes} 30 -1040 0 0 0.4 0.4 { layer=4 slant=oblique}
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T {Instance based
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implementation selection.} 100 -1140 0 0 0.8 0.8 {}
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T {comp3_read.sym:
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symbol has "spice_sym_def"
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attribute and reads in a file} 340 -360 0 0 0.4 0.4 { layer=13}
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attribute and reads in a file} 740 -410 0 0 0.4 0.4 { layer=13}
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T {Alternate instance:
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Uses comp3_pex2
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referenced by a
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.include comp3_pex2.cir
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in spice_sym_def
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No schematic used} 10 -500 0 0 0.4 0.4 { layer=10}
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C {comp3.sym} 180 -1080 0 0 {name=x1}
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C {comp3.sym} 180 -870 0 0 {name=x2
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T {Symbol based
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implementation selection.} 650 -530 2 1 0.8 0.8 {}
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T {The 'spice_sym_def ' attribute is defined inside the
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symbol, this applies to all placements of this symbol} 640 -510 0 0 0.4 0.4 { layer=4 slant=oblique}
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T {In all cases where an external netlist file
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is provided either directly or by a .include
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line xschem will adapt port order of instances
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to match the port order of the provided
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netlists.} 620 -940 0 0 0.5 0.5 {}
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C {comp3.sym} 480 -840 0 0 {name=x1}
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C {comp3.sym} 180 -850 0 0 {name=x2
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schematic=comp3_parax.sch}
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C {comp3.sym} 180 -600 0 0 {name=x3
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C {comp3.sym} 180 -580 0 0 {name=x3
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schematic=comp3_pex
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spice_sym_def=".subckt comp3_pex MINUS PLUS OUT
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** parasitic netlist
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@ -140,9 +150,9 @@ spice_sym_def="tcleval(.include [abs_sym_path comp3_pex2.cir])"
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verilog_sym_def="verilog stuff"
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vhdl_sym_def="vhdl stuff"}
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C {comp3.sym} 490 -730 0 0 {name=x5
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C {comp3.sym} 480 -580 0 0 {name=x5
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schematic=comp3_empty.sch}
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C {comp3.sym} 490 -450 0 0 {name=x6
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C {comp3.sym} 480 -280 0 0 {name=x6
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schematic=comp3_file
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spice_sym_def="tcleval(
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[read_data_nonewline [abs_sym_path comp3_file.cir]]
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@ -152,17 +162,17 @@ vhdl_sym_def="tcleval(
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[read_data_nonewline [abs_sym_path comp3_file.cir]]
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)"
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tclcommand="textwindow [abs_sym_path comp3_file.cir]"}
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C {comp3_read.sym} 490 -230 0 0 {name=x7
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C {comp3_read.sym} 890 -280 0 0 {name=x7
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tclcommand="textwindow [abs_sym_path comp3_read.cir]"}
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C {lab_pin.sym} 240 -1080 0 1 {name=p2 lab=OUT1}
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C {lab_pin.sym} 240 -870 0 1 {name=p5 lab=OUT2}
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C {lab_pin.sym} 240 -600 0 1 {name=p8 lab=OUT3}
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C {lab_pin.sym} 540 -840 0 1 {name=p2 lab=OUT1}
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C {lab_pin.sym} 240 -850 0 1 {name=p5 lab=OUT2}
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C {lab_pin.sym} 240 -580 0 1 {name=p8 lab=OUT3}
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C {lab_pin.sym} 240 -290 0 1 {name=p35 lab=OUT4}
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C {lab_pin.sym} 550 -730 0 1 {name=p16 lab=OUT5}
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C {lab_pin.sym} 550 -450 0 1 {name=p19 lab=OUT6}
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C {lab_pin.sym} 550 -230 0 1 {name=p23 lab=OUT7}
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C {lab_pin.sym} 120 -840 0 0 {name=p6 lab=MINUS}
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C {lab_pin.sym} 540 -580 0 1 {name=p16 lab=OUT5}
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C {lab_pin.sym} 540 -280 0 1 {name=p19 lab=OUT6}
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C {lab_pin.sym} 950 -280 0 1 {name=p23 lab=OUT7}
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C {lab_pin.sym} 120 -820 0 0 {name=p6 lab=MINUS}
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C {lab_pin.sym} 700 -90 0 0 {name=p10 lab=0}
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C {vsource.sym} 820 -120 0 0 {name=V2 value=1
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savecurrent=true}
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@ -173,7 +183,7 @@ savecurrent=true}
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C {lab_pin.sym} 970 -150 0 0 {name=p13 lab=PLUS}
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C {lab_pin.sym} 970 -90 0 0 {name=p14 lab=0}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {launcher.sym} 820 -190 0 0 {name=h5
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C {launcher.sym} 1380 -40 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/test_instance_schematic_selection.raw tran"
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}
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@ -183,8 +193,8 @@ C {code_shown.sym} 140 -170 0 0 {name=COMMANDS only_toplevel=false value=".contr
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write test_instance_schematic_selection.raw
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.endc
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"}
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C {lab_pin.sym} 120 -1110 0 0 {name=p1 lab=PLUS}
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C {lab_pin.sym} 430 -760 0 0 {name=p15 lab=PLUS}
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C {lab_pin.sym} 420 -870 0 0 {name=p1 lab=PLUS}
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C {lab_pin.sym} 420 -610 0 0 {name=p15 lab=PLUS}
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C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version released on 2/22/06
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* PTM 65nm NMOS
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@ -311,17 +321,17 @@ C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version r
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+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
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+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
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"}
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C {lab_pin.sym} 430 -700 0 0 {name=p17 lab=MINUS}
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C {lab_pin.sym} 120 -900 0 0 {name=p4 lab=PLUS}
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C {lab_pin.sym} 430 -480 0 0 {name=p18 lab=PLUS}
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C {lab_pin.sym} 420 -550 0 0 {name=p17 lab=MINUS}
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C {lab_pin.sym} 120 -880 0 0 {name=p4 lab=PLUS}
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C {lab_pin.sym} 420 -310 0 0 {name=p18 lab=PLUS}
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C {vsource.sym} 700 -120 0 0 {name=V1 value=2
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savecurrent=true}
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C {lab_pin.sym} 430 -420 0 0 {name=p20 lab=MINUS}
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C {lab_pin.sym} 120 -630 0 0 {name=p7 lab=PLUS}
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C {lab_pin.sym} 430 -260 0 0 {name=p22 lab=PLUS}
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C {lab_pin.sym} 420 -250 0 0 {name=p20 lab=MINUS}
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C {lab_pin.sym} 120 -610 0 0 {name=p7 lab=PLUS}
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C {lab_pin.sym} 830 -310 0 0 {name=p22 lab=PLUS}
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C {lab_pin.sym} 700 -150 0 0 {name=p21 lab=VCC}
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C {lab_pin.sym} 430 -200 0 0 {name=p24 lab=MINUS}
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C {lab_pin.sym} 120 -1050 0 0 {name=p3 lab=MINUS}
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C {lab_pin.sym} 830 -250 0 0 {name=p24 lab=MINUS}
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C {lab_pin.sym} 420 -810 0 0 {name=p3 lab=MINUS}
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C {lab_pin.sym} 120 -320 0 0 {name=p34 lab=PLUS}
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C {lab_pin.sym} 120 -570 0 0 {name=p9 lab=MINUS}
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C {lab_pin.sym} 120 -550 0 0 {name=p9 lab=MINUS}
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C {lab_pin.sym} 120 -260 0 0 {name=p36 lab=MINUS}
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