xschem/xschem_library/pcb/si2306.sym

v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=pmos
format="@name @pinlist @model m=@m"
template="name=m1 model=dmp2035u m=1"
verilog_format="@symname #@del @name ( @@d , @@s , @@g );"}
V {}
S {}
E {}
L 4 5 -27.5 5 27.5 {}
L 4 5 20 20 20 {}
L 4 20 20 20 30 {}
L 4 5 -20 20 -20 {}
L 4 20 -30 20 -20 {}
L 4 -5 -15 -5 15 {}
L 4 -5 -5 -5 -0 {}
L 4 -7.5 -5 -5 -2.5 {}
L 4 -10 -5 -7.5 -5 {}
L 4 -12.5 -2.5 -10 -5 {}
L 4 -12.5 -2.5 -12.5 2.5 {}
L 4 -12.5 2.5 -10 5 {}
L 4 -10 5 -7.5 5 {}
L 4 -7.5 5 -5 2.5 {}
L 4 -20 0 -12.5 -0 {}
B 5 17.5 27.5 22.5 32.5 {name=d dir=inout}
B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout}
T {@model} 7.5 -17.5 0 0 0.2 0.2 {}
T {@name} 7.5 0 0 0 0.2 0.2 {}
T {D} 22.5 12.5 0 0 0.2 0.2 {}