xschem/xschem_library/pcb/pcb_test2.sch

v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {}
V {}
S {}
E {}
C {title.sym} 160 -30 0 0 {name=l2 author="Stefan"}
C {74ls00-2.sym} 320 -280 0 0 {name=U\\\\\\ 5:3
url="http://www.engrcs.com/components/74LS00.pdf"}
C {74ls00-2.sym} 230 -450 0 0 {name=U\\\\\\ 5:1 pippo=ccc\\ ddd
url="http://www.engrcs.com/components/74LS00.pdf"
}
C {lab_pin.sym} 280 -300 0 0 {name=p1 lab=U51_A}
C {lab_pin.sym} 280 -260 0 0 {name=p2 lab=U51_B}
C {lab_pin.sym} 380 -280 0 1 {name=p3 lab=U51_Z}
C {lab_pin.sym} 320 -330 0 0 {name=p4 lab=VCC}
C {lab_pin.sym} 320 -230 0 0 {name=p5 lab=GND}
C {lab_pin.sym} 190 -470 0 0 {name=p6 lab=U53_A}
C {lab_pin.sym} 190 -430 0 0 {name=p7 lab=U53_B}
C {lab_pin.sym} 290 -450 0 1 {name=p8 lab=U53_Z}
C {lab_pin.sym} 230 -500 0 0 {name=p9 lab=VCC}
C {lab_pin.sym} 230 -400 0 0 {name=p10 lab=GND}