xschem/xschem_library/devices/port_attributes.sym

v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=port_attributes
spice_ignore=true
verilog_ignore=true
tedax_ignore=true
template="
 attribute async_set_reset of RPTL : signal is "true";
"}
V {}
S {}
E {}
L 4 -0 -10 355 -10 {}
T {VHDL PORT ATTRIBUTES} 5 -25 0 0 0.3 0.3 {}
T {@prop_ptr} 45 5 0 0 0.2 0.2 {}