32 lines
719 B
Plaintext
32 lines
719 B
Plaintext
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v {xschem version=2.9.5_RC5 file_version=1.1}
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G {
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a: process( CK , RST )
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begin
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if ( RST = '1' ) then
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Q <= '0' after delay ;
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elsif CK'event AND CK = '1' then
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Q <= D after delay ;
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end if ;
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end process ;
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}
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V {reg iQ;
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always @(posedge CK or posedge RST) begin
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if(RST) iQ=0;
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else iQ=D;
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end
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assign #del Q=iQ;
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}
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S {}
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E {}
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C {ipin.sym} 60 -150 0 0 {name=p1 lab=D}
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C {opin.sym} 130 -130 0 0 {name=p2 verilog_type=wire lab=Q}
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C {ipin.sym} 60 -130 0 0 {name=p3 lab=CK}
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C {ipin.sym} 60 -110 0 0 {name=p5 lab=RST}
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C {title.sym} 160 -30 0 0 {name=l2}
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C {use.sym} 100 -440 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;}
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