xschem/xschem_library/logic/sync_reg.sym

v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
verilog_stop=true
format="@name @pinlist @symname"
template="name=x1 width=8 del=400 delay=\\"400 ps\\""
generic_type="delay=time"
}
V {}
S {}
E {}
L 4 -80 -40 80 -40 {}
L 4 -80 40 80 40 {}
L 4 -80 -40 -80 40 {}
L 4 80 -40 80 40 {}
L 4 80 -30 100 -30 {}
L 4 -100 30 -80 30 {}
L 4 -100 10 -80 10 {}
L 4 -100 -30 -80 -30 {}
L 4 -100 -10 -80 -10 {}
B 5 97.5 -32.5 102.5 -27.5 {name=DATA_OUT[width-1:0] sig_type=std_logic verilog_type=wire dir=out }
B 5 -102.5 27.5 -97.5 32.5 {name=CK sig_type=std_logic verilog_type=wire dir=in }
B 5 -102.5 7.5 -97.5 12.5 {name=RESET sig_type=std_logic verilog_type=wire dir=in }
B 5 -102.5 -32.5 -97.5 -27.5 {name=DATA_IN[width-1:0] sig_type=std_logic verilog_type=wire dir=in }
B 5 -102.5 -12.5 -97.5 -7.5 {name=LOAD sig_type=std_logic verilog_type=wire dir=in }
T {@symname} -40.5 19 0 0 0.3 0.3 {}
T {@name} 85 -52 0 0 0.2 0.2 {}
T {DATA_OUT} 75 -34 0 1 0.2 0.2 {}
T {CK} -75 26 0 0 0.2 0.2 {}
T {RESET} -75 6 0 0 0.2 0.2 {}
T {DATA_IN} -75 -34 0 0 0.2 0.2 {}
T {LOAD} -75 -14 0 0 0.2 0.2 {}
T {width=@width} -55 -54 0 0 0.2 0.2 {}