2023-10-09 12:49:11 +02:00
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v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2023 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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2020-08-08 15:47:34 +02:00
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G {}
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V {}
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S {}
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E {}
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N 100 -800 150 -800 {lab=#net1}
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N 150 -800 150 -780 {lab=#net1}
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N 150 -780 210 -780 {lab=#net1}
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C {nand2.sym} 260 -760 0 0 {name=x1 WP=12u LP=0.4u WN=8u LN=0.6u}
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C {nand2.sym} 50 -800 0 0 {name=x2 WP=5u LP=1u WN=3u LN=1.5u}
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C {lab_pin.sym} 0 -820 0 0 {name=p1 lab=A}
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C {lab_pin.sym} 0 -780 0 0 {name=p2 lab=B}
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C {lab_pin.sym} 310 -760 0 1 {name=p3 lab=Z}
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C {lab_pin.sym} 210 -740 0 0 {name=p4 lab=C}
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