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Yilou Wangandgithub action
cfebe805c9
* Support implication operator with constraint_set * improve coverage, achieve 100 line cov * Address review: simplify addNext; tighten disable soft grammar to constraint_primary * Apply 'make format' * re-run --------- Co-authored-by: github action <[email protected]>
24 lines
581 B
Systemverilog
24 lines
581 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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class C;
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rand bit [3:0] a;
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rand bit [3:0] b;
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// IEEE 1800-2023 18.7.2: implication operator -> takes one constraint_set
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// on the RHS; it is single-armed (no else clause). Only the if (...) form
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// accepts an optional else branch.
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constraint c_bad {
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(a == 0) -> { b == 4'h1; } else { b == 4'h2; }
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}
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endclass
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module t;
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initial begin
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$stop;
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end
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endmodule
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