* Support implication operator with constraint_set * improve coverage, achieve 100 line cov * Address review: simplify addNext; tighten disable soft grammar to constraint_primary * Apply 'make format' * re-run --------- Co-authored-by: github action <action@example.com>
This commit is contained in:
Yilou Wang
GitHub
parent
46a6884df6
commit
cfebe805c9
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@ -2007,6 +2007,10 @@ class ConstraintExprVisitor final : public VNVisitor {
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void visit(AstSFormatF* nodep) override {}
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void visit(AstStmtExpr* nodep) override {}
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void visit(AstCStmt* nodep) override {}
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void visit(AstIf* nodep) override {
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// Hoisted runtime-conditional disable_soft statements parked in the
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// constraint-items list by the pre-pass; already fully lowered.
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}
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void visit(AstConstraintIf* nodep) override {
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AstNodeExpr* newp = nullptr;
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FileLine* const fl = nodep->fileline();
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@ -2192,28 +2196,13 @@ class ConstraintExprVisitor final : public VNVisitor {
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}
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void visit(AstConstraintExpr* nodep) override {
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// IEEE 1800-2023 18.5.13: "disable soft" removes all soft constraints
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// referencing the specified variable. Pass the variable name directly
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// instead of going through SMT lowering.
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// IEEE 1800-2023 18.5.13: 'disable soft' is a meta-level directive on
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// the constraint graph, lowered to a void RANDOMIZER_DISABLE_SOFT
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// call. Conditional occurrences (if / foreach / implication body)
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// are rewritten by extractConditionalDisableSofts() before this
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// visitor runs, so anything we see here is unconditional.
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if (nodep->isDisableSoft()) {
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// Extract variable name from expression (VarRef or MemberSel)
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std::string varName;
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if (const AstNodeVarRef* const vrefp = VN_CAST(nodep->exprp(), NodeVarRef)) {
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varName = vrefp->name();
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} else if (const AstMemberSel* const mselp = VN_CAST(nodep->exprp(), MemberSel)) {
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varName = mselp->name();
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} else {
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nodep->v3fatalSrc("Unexpected expression type in disable soft");
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return;
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}
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AstCMethodHard* const callp = new AstCMethodHard{
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nodep->fileline(),
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new AstVarRef{nodep->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp,
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VAccess::READWRITE},
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VCMethod::RANDOMIZER_DISABLE_SOFT,
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new AstConst{nodep->fileline(), AstConst::String{}, varName}};
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callp->dtypeSetVoid();
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nodep->replaceWith(callp->makeStmt());
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nodep->replaceWith(buildDisableSoftCallStmt(nodep));
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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return;
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}
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@ -2603,6 +2592,93 @@ class ConstraintExprVisitor final : public VNVisitor {
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"Visit function missing? Constraint function missing for node: " << nodep);
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}
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// Build the runtime statement that calls RANDOMIZER_DISABLE_SOFT on the
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// variable referenced by the given AstConstraintExpr. Parser enforces
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// constraint_primary operand (verilog.y, IEEE 1800-2023 18.5.13).
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AstNode* buildDisableSoftCallStmt(AstConstraintExpr* nodep) {
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std::string varName;
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if (const AstNodeVarRef* const vrefp = VN_CAST(nodep->exprp(), NodeVarRef)) {
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varName = vrefp->name();
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} else if (const AstMemberSel* const mselp = VN_CAST(nodep->exprp(), MemberSel)) {
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varName = mselp->name();
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} else {
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nodep->v3fatalSrc("Unexpected expression type in disable soft");
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}
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AstCMethodHard* const callp = new AstCMethodHard{
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nodep->fileline(),
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new AstVarRef{nodep->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp,
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VAccess::READWRITE},
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VCMethod::RANDOMIZER_DISABLE_SOFT,
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new AstConst{nodep->fileline(), AstConst::String{}, varName}};
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callp->dtypeSetVoid();
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return callp->makeStmt();
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}
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// Pre-pass: for every AstConstraintExpr(isDisableSoft) nested inside an
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// AstConstraintIf subtree (any depth), return a list of runtime AstIf
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// statements `if (accumulated_cond) randomizer.disable_soft(var);` where
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// accumulated_cond AND-folds the enclosing then/else branch conditions.
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// The original ConstraintExpr is replaced with `1'b1` so editSingle()
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// folds the surrounding boolean cleanly. Caller appends the returned
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// list to the constraint-items chain; that chain becomes the setup task
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// body, which runs before the solver on every randomize() call -- giving
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// disable-soft real conditional semantics per IEEE 1800-2023 18.5.13.
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AstNode* extractConditionalDisableSofts(AstNode* itemsp, AstNodeExpr* outerCondp) {
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AstNode* hoistListp = nullptr;
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for (AstNode *stmtp = itemsp, *nextp; stmtp; stmtp = nextp) {
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nextp = stmtp->nextp();
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if (AstConstraintIf* const ifp = VN_CAST(stmtp, ConstraintIf)) {
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FileLine* const fl = ifp->fileline();
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// then branch: accumulated = outer && this.cond
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AstNodeExpr* const thenCondp
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= outerCondp ? static_cast<AstNodeExpr*>(
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new AstLogAnd{fl, outerCondp->cloneTreePure(false),
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ifp->condp()->cloneTreePure(false)})
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: ifp->condp()->cloneTreePure(false);
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if (AstNode* const thenHoistp
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= extractConditionalDisableSofts(ifp->thensp(), thenCondp)) {
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hoistListp
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= hoistListp ? AstNode::addNext(hoistListp, thenHoistp) : thenHoistp;
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}
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VL_DO_DANGLING(thenCondp->deleteTree(), thenCondp);
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if (ifp->elsesp()) {
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// else branch: accumulated = outer && !this.cond
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AstNodeExpr* const notInnerp
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= new AstLogNot{fl, ifp->condp()->cloneTreePure(false)};
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AstNodeExpr* const elseCondp
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= outerCondp ? static_cast<AstNodeExpr*>(new AstLogAnd{
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fl, outerCondp->cloneTreePure(false), notInnerp})
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: notInnerp;
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if (AstNode* const elseHoistp
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= extractConditionalDisableSofts(ifp->elsesp(), elseCondp)) {
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hoistListp
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= hoistListp ? AstNode::addNext(hoistListp, elseHoistp) : elseHoistp;
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}
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VL_DO_DANGLING(elseCondp->deleteTree(), elseCondp);
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}
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} else if (AstConstraintExpr* const exprp = VN_CAST(stmtp, ConstraintExpr)) {
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if (exprp->isDisableSoft() && outerCondp) {
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FileLine* const fl = exprp->fileline();
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AstIf* const hoistIfp = new AstIf{fl, outerCondp->cloneTreePure(false),
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buildDisableSoftCallStmt(exprp), nullptr};
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hoistListp = hoistListp ? AstNode::addNext(hoistListp,
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static_cast<AstNode*>(hoistIfp))
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: static_cast<AstNode*>(hoistIfp);
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// Replace in-tree disable-soft with a no-op boolean
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// constraint so editSingle() folds cleanly.
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AstConstraintExpr* const truep
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= new AstConstraintExpr{fl, new AstConst{fl, AstConst::BitTrue{}}};
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exprp->replaceWith(truep);
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VL_DO_DANGLING(exprp->deleteTree(), exprp);
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}
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}
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// foreach/unique bodies are left untouched: disable-soft inside
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// a foreach would need per-iteration condition support, and
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// unique cannot legally contain disable-soft.
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}
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return hoistListp;
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}
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public:
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// CONSTRUCTORS
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explicit ConstraintExprVisitor(AstClass* classp, VMemberMap& memberMap, AstNode* nodep,
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@ -2618,6 +2694,14 @@ public:
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, m_memberMap{memberMap}
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, m_writtenVars{writtenVars}
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, m_sizeConstrainedArraysp{sizeConstrainedArraysp} {
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// Pre-pass before SMT lowering: extract conditional disable-soft
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// directives as runtime AstIf statements and append them to the
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// constraint-items chain so they reach the setup task body. The SMT
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// visitor skips these via visit(AstIf) above.
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if (AstNode* const hoistListp
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= nodep ? extractConditionalDisableSofts(nodep, nullptr) : nullptr) {
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nodep->addNext(hoistListp);
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}
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iterateAndNextNull(nodep);
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}
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};
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@ -5085,11 +5085,11 @@ expr<nodeExprp>: // IEEE: part of expression/constant_expression/
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| type_referenceEq yP_EQUAL type_referenceBoth { $$ = new AstEqT{$2, $1, $3}; }
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| type_referenceEq yP_NOTEQUAL type_referenceBoth { $$ = new AstNeqT{$2, $1, $3}; }
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// // IEEE: expr yP_MINUSGT expr (1800-2009)
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// // Conflicts with constraint_expression:"expr yP_MINUSGT constraint_set"
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// // To duplicating expr for constraints, just allow the more general form
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// // Later Ast processing must ignore constraint terms where inappropriate
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//UNSUP ~l~expr yP_MINUSGT constraint_set { $<fl>$ = $<fl>1; $$ = $1 + $2 + $3; }
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//UNSUP remove line below
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// // Full IEEE 1800-2023 18.7.2 "expr ->
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// // constraint_set" is split: this rule handles
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// // the bare-expression RHS as a boolean
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// // (AstLogIf), constraint_expression has one
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// // production per non-expression RHS shape.
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| ~l~expr yP_MINUSGT ~r~expr { $$ = new AstLogIf{$2, $1, $3}; }
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//
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// // <= is special, as we need to disambiguate it with <= assignment
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@ -7910,8 +7910,37 @@ constraint_expression<nodep>: // ==IEEE: constraint_expression
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| yUNIQUE '{' range_list '}' ';'
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{ $$ = new AstConstraintUnique{$1, $3}; }
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// // IEEE: expr yP_MINUSGT constraint_set
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// // Conflicts with expr:"expr yP_MINUSGT expr"; rule moved there
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//
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// // The bare-expression case "expr -> expr ;"
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// // arrives via the general expr rule above
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// // (AstLogIf) and matches "expr ';'". Each
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// // production below covers one constraint_set
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// // shape that is not a plain expression and
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// // builds an outer AstConstraintIf wrapping the
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// // statement V3Randomize already knows how to
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// // lower (with disable-soft hoisted by the
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// // ConstraintExprVisitor pre-pass).
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| expr yP_MINUSGT '{' constraint_expressionList '}'
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{ $$ = new AstConstraintIf{$2, $1, $4, nullptr}; }
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| expr yP_MINUSGT yIF '(' expr ')' constraint_set %prec prLOWER_THAN_ELSE
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{ $$ = new AstConstraintIf{$2, $1,
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new AstConstraintIf{$3, $5, $7, nullptr}, nullptr}; }
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| expr yP_MINUSGT yIF '(' expr ')' constraint_set yELSE constraint_set
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{ $$ = new AstConstraintIf{$2, $1,
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new AstConstraintIf{$3, $5, $7, $9}, nullptr}; }
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| expr yP_MINUSGT yFOREACH '(' idClassSelForeach ')' constraint_set
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{ $$ = new AstConstraintIf{$2, $1,
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new AstConstraintForeach{$3, $5, $7}, nullptr}; }
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| expr yP_MINUSGT yUNIQUE '{' range_list '}' ';'
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{ $$ = new AstConstraintIf{$2, $1,
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new AstConstraintUnique{$3, $5}, nullptr}; }
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| expr yP_MINUSGT ySOFT expr ';'
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{ AstConstraintExpr* const innerp = new AstConstraintExpr{$3, $4};
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innerp->isSoft(true);
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$$ = new AstConstraintIf{$2, $1, innerp, nullptr}; }
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| expr yP_MINUSGT yDISABLE ySOFT constraint_primary ';'
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{ AstConstraintExpr* const innerp = new AstConstraintExpr{$3, $5};
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innerp->isDisableSoft(true);
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$$ = new AstConstraintIf{$2, $1, innerp, nullptr}; }
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| yIF '(' expr ')' constraint_set %prec prLOWER_THAN_ELSE
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{ $$ = new AstConstraintIf{$1, $3, $5, nullptr}; }
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| yIF '(' expr ')' constraint_set yELSE constraint_set
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@ -7920,7 +7949,7 @@ constraint_expression<nodep>: // ==IEEE: constraint_expression
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| yFOREACH '(' idClassSelForeach ')' constraint_set
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{ $$ = new AstConstraintForeach{$1, $3, $5}; }
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// // soft is 1800-2012
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| yDISABLE ySOFT expr/*constraint_primary*/ ';'
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| yDISABLE ySOFT constraint_primary ';'
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{ AstConstraintExpr* const newp = new AstConstraintExpr{$1, $3};
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newp->isDisableSoft(true);
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$$ = newp; }
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@ -0,0 +1,5 @@
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%Error: t/t_constraint_disable_soft_bad.v:15:25: syntax error, unexpected ';'
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15 | disable soft (a + 1);
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| ^
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,23 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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class C;
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rand bit [3:0] a;
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rand bit [3:0] b;
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// IEEE 1800-2023 18.5.13: the operand of 'disable soft' must be a
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// constraint_primary (hierarchical identifier with optional select),
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// not a bare expression such as (a + 1).
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constraint c_bad {
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disable soft (a + 1);
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}
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endclass
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module t;
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initial begin
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$stop;
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end
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endmodule
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@ -0,0 +1,5 @@
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%Error: t/t_constraint_implication_else_bad.v:15:32: syntax error, unexpected else
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15 | (a == 0) -> { b == 4'h1; } else { b == 4'h2; }
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| ^~~~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,23 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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class C;
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rand bit [3:0] a;
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rand bit [3:0] b;
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// IEEE 1800-2023 18.7.2: implication operator -> takes one constraint_set
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// on the RHS; it is single-armed (no else clause). Only the if (...) form
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// accepts an optional else branch.
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constraint c_bad {
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(a == 0) -> { b == 4'h1; } else { b == 4'h2; }
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}
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endclass
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module t;
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initial begin
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$stop;
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end
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endmodule
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|
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
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#
|
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# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of either the GNU Lesser General Public License Version 3
|
||||
# or the Perl Artistic License Version 2.0.
|
||||
# SPDX-FileCopyrightText: 2026 Wilson Snyder
|
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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if not test.have_solver:
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test.skip("No constraint solver installed")
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test.compile()
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test.execute()
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test.passes()
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|
|
@ -0,0 +1,254 @@
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// DESCRIPTION: Verilator: Verilog Test module
|
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//
|
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
|
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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typedef enum bit [1:0] { TXN_READ, TXN_WRITE } txn_e;
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// Each constraint exercises one RHS shape allowed by IEEE 1800-2023 18.7.2
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// (constraint_set on the right of the implication operator -> ). `mode`
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// selects which constraint contributes; the others are vacuous.
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class Forms;
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rand bit [3:0] mode;
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rand bit [3:0] a;
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rand bit [3:0] b;
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rand bit [3:0] c;
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rand bit [31:0] address;
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rand txn_e txn_type;
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rand bit [7:0] arr [4];
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rand bit [3:0] uarr [3];
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// Bare expression (legacy form, supported pre-PR via expr->expr).
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constraint c_expr {
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(mode == 4'd0) -> b == 4'h9;
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}
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// Brace-block: the exact shape from issue #7300.
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constraint c_brace_repro {
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(mode == 4'd1) -> {
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if (txn_type inside {TXN_READ}) address % (1 << 4) == 0;
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}
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}
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// Brace-block with multiple statements.
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constraint c_brace_multi {
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(mode == 4'd2) -> {
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address[0] == 1'b0;
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address[31] == 1'b0;
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}
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}
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// Bare if (without surrounding braces).
|
||||
constraint c_if {
|
||||
(mode == 4'd3) -> if (a == 4'h1) b == 4'h7;
|
||||
}
|
||||
|
||||
// Bare if/else.
|
||||
constraint c_if_else {
|
||||
(mode == 4'd4) -> if (a == 4'h1) b == 4'ha;
|
||||
else b == 4'hb;
|
||||
}
|
||||
|
||||
// Bare foreach.
|
||||
constraint c_foreach {
|
||||
(mode == 4'd5) -> foreach (arr[i]) arr[i] < 8'h40;
|
||||
}
|
||||
|
||||
// Bare unique (uses the static-array form V3Randomize supports today).
|
||||
constraint c_unique {
|
||||
(mode == 4'd6) -> unique { uarr };
|
||||
}
|
||||
|
||||
// Bare soft.
|
||||
constraint c_soft {
|
||||
(mode == 4'd7) -> soft b == 4'hd;
|
||||
}
|
||||
|
||||
// Nested implication inside a brace block.
|
||||
constraint c_nested {
|
||||
(mode == 4'd8) -> {
|
||||
(a == 4'h0) -> { b == 4'h5; }
|
||||
}
|
||||
}
|
||||
endclass
|
||||
|
||||
// Conditional `disable soft` is meta-level: V3Randomize hoists it into a
|
||||
// runtime AstIf attached to the setup task so the directive only fires
|
||||
// when its outer condition is true. When override_flag==0, the soft
|
||||
// `x == 4'h5` wins; when override_flag==1, the implication fires the
|
||||
// disable AND the override `x == 4'hc`, so x must be 4'hc.
|
||||
class DisSoft;
|
||||
bit override_flag;
|
||||
rand bit [3:0] x;
|
||||
constraint c_soft_x { soft x == 4'h5; }
|
||||
constraint c_override {
|
||||
(override_flag == 1'b1) -> disable soft x ;
|
||||
(override_flag == 1'b1) -> x == 4'hc ;
|
||||
}
|
||||
endclass
|
||||
|
||||
// MemberSel target for `disable soft`. Cross-object reference (inner.y)
|
||||
// parses as AstMemberSel; disable-soft must extract the variable name from
|
||||
// that node shape too.
|
||||
class Inner;
|
||||
rand bit [3:0] y;
|
||||
endclass
|
||||
class DisSoftMember;
|
||||
bit override_flag;
|
||||
rand Inner inner;
|
||||
constraint c_soft_y { soft inner.y == 4'h5; }
|
||||
constraint c_override {
|
||||
(override_flag == 1'b1) -> disable soft inner.y ;
|
||||
(override_flag == 1'b1) -> inner.y == 4'hc ;
|
||||
}
|
||||
function new(); inner = new(); endfunction
|
||||
endclass
|
||||
|
||||
// `disable soft` in BOTH then and else arms of a single if. Exercises the
|
||||
// hoist-list concat path in the else branch (a then-arm hoist already
|
||||
// exists when the else-arm hoist is appended). We only check that the
|
||||
// hard constraint in each arm fires correctly under its `pick` condition;
|
||||
// soft enforcement priority is not asserted (Verilator's soft solver is
|
||||
// best-effort). The condition variable `pick` is non-rand so the setup
|
||||
// task sees its current value before the solver runs.
|
||||
class DisSoftBothArms;
|
||||
bit [1:0] pick;
|
||||
rand bit [3:0] a;
|
||||
rand bit [3:0] b;
|
||||
constraint c_soft_a { soft a == 4'h7; }
|
||||
constraint c_soft_b { soft b == 4'h8; }
|
||||
constraint c_split {
|
||||
if (pick == 2'd0) { disable soft a; a == 4'h1; }
|
||||
else { disable soft b; b == 4'h2; }
|
||||
}
|
||||
endclass
|
||||
|
||||
module t;
|
||||
Forms obj;
|
||||
DisSoft ds;
|
||||
int ok;
|
||||
|
||||
initial begin
|
||||
obj = new();
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd0; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.b, 4'h9);
|
||||
end
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd1; txn_type == TXN_READ; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.address[3:0], 4'h0);
|
||||
end
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd2; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.address[0], 1'b0);
|
||||
`checkh(obj.address[31], 1'b0);
|
||||
end
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd3; a == 4'h1; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.b, 4'h7);
|
||||
end
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd4; a == 4'h1; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.b, 4'ha);
|
||||
end
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd4; a == 4'h2; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.b, 4'hb);
|
||||
end
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd5; };
|
||||
`checkd(ok, 1);
|
||||
foreach (obj.arr[i]) `checkh(obj.arr[i] < 8'h40, 1'b1);
|
||||
end
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd6; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.uarr[0] == obj.uarr[1], 1'b0);
|
||||
`checkh(obj.uarr[0] == obj.uarr[2], 1'b0);
|
||||
`checkh(obj.uarr[1] == obj.uarr[2], 1'b0);
|
||||
end
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd7; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.b, 4'hd);
|
||||
end
|
||||
|
||||
repeat (10) begin
|
||||
ok = obj.randomize() with { mode == 4'd8; a == 4'h0; };
|
||||
`checkd(ok, 1);
|
||||
`checkh(obj.b, 4'h5);
|
||||
end
|
||||
|
||||
ds = new();
|
||||
ds.override_flag = 1'b0;
|
||||
repeat (10) begin
|
||||
ok = ds.randomize();
|
||||
`checkd(ok, 1);
|
||||
`checkh(ds.x, 4'h5);
|
||||
end
|
||||
ds.override_flag = 1'b1;
|
||||
repeat (10) begin
|
||||
ok = ds.randomize();
|
||||
`checkd(ok, 1);
|
||||
`checkh(ds.x, 4'hc);
|
||||
end
|
||||
|
||||
begin
|
||||
automatic DisSoftMember dsm = new();
|
||||
dsm.override_flag = 1'b0;
|
||||
repeat (10) begin
|
||||
ok = dsm.randomize();
|
||||
`checkd(ok, 1);
|
||||
`checkh(dsm.inner.y, 4'h5);
|
||||
end
|
||||
dsm.override_flag = 1'b1;
|
||||
repeat (10) begin
|
||||
ok = dsm.randomize();
|
||||
`checkd(ok, 1);
|
||||
`checkh(dsm.inner.y, 4'hc);
|
||||
end
|
||||
end
|
||||
|
||||
begin
|
||||
automatic DisSoftBothArms dba = new();
|
||||
// pick==0: hard a==1 fires (then arm); hoisted disable_soft(a) runs
|
||||
dba.pick = 2'd0;
|
||||
repeat (10) begin
|
||||
ok = dba.randomize();
|
||||
`checkd(ok, 1);
|
||||
`checkh(dba.a, 4'h1);
|
||||
end
|
||||
// pick==1: hard b==2 fires (else arm); hoisted disable_soft(b) runs
|
||||
dba.pick = 2'd1;
|
||||
repeat (10) begin
|
||||
ok = dba.randomize();
|
||||
`checkd(ok, 1);
|
||||
`checkh(dba.b, 4'h2);
|
||||
end
|
||||
end
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue