12 lines
340 B
Plaintext
12 lines
340 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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clock_enable --module "t" --var "clk"
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clocker --module "t" --var "clk"
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no_clocker --module "t" --var "clk"
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