// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

`verilator_config

clock_enable --module "t" --var "clk"
clocker --module "t" --var "clk"
no_clocker --module "t" --var "clk"