51 lines
1.1 KiB
Systemverilog
51 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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reg [1:0] a = 0, b = 1;
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reg [1:0] r;
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initial begin
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r = 2'b00;
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assign r = 2'b01;
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`checkb(r, 2'b01)
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r = 2'b00; // ignored
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#1;
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`checkb(r, 2'b01)
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deassign r;
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`checkb(r, 2'b01)
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r = 2'b00;
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`checkb(r, 2'b00)
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assign r = a;
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`checkb(r, 2'b00)
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a = 2'b01;
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`checkb(r, 2'b01)
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a = 2'b00;
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`checkb(r, 2'b00)
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force r = a + b;
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a = 2'b00;
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b = 2'b00;
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#1;
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`checkb(r, 2'b00)
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a = 2'b01;
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b = 2'b01;
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#1;
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`checkb(r, 2'b10)
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assign r = b; // covered
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r = 2'b11; // ignored
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`checkb(r, 2'b10)
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release r;
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`checkb(r, 2'b01)
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b = 2'b00;
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`checkb(r, 2'b00)
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$finish;
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end
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endmodule
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