4 Commits

Author	SHA1	Message	Date
Wilson Snyder	1653b982b9	Verilog format	2026-05-13 21:00:34 -04:00
Artur Bieniek	c69c11b2db	Support procedural continuous assign/deassign (#7493)	2026-05-08 19:01:11 -04:00
Wilson Snyder	7c6c6a684b	Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.	2026-01-26 20:24:34 -05:00
Bartłomiej Chmiel	a379382d32	Fix handling forced assigns in V3Life (#5757)	2025-01-28 07:30:40 -05:00