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56 lines
1.0 KiB
Systemverilog
56 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic clk = 1'b0;
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// verilog_format: off
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property c_prop;
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@(negedge clk)
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1'b1;
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endproperty : c_prop
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property asrt_prop;
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@(negedge clk)
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1'b1;
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endproperty : asrt_prop
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property assm_prop;
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@(negedge clk)
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1'b1;
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endproperty : assm_prop
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sequence seq;
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1'b1;
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endsequence : seq
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property prop_seq;
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@(negedge clk) seq;
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endproperty : prop_seq
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property inner_prop;
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@(negedge clk)
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1'b1;
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endproperty : inner_prop
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property outer_prop;
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inner_prop;
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endproperty : outer_prop
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cover property (c_prop);
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assert property (asrt_prop);
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assume property (assm_prop);
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cover property (prop_seq);
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cover property (outer_prop);
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always #1 clk = ~clk;
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initial begin
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repeat (3) @(posedge clk);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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