132 lines
1.9 KiB
Systemverilog
132 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t (
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input clk
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);
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integer cyc = 0;
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wire out;
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reg in;
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Genit g (
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.clk(clk),
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.value(in),
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.result(out)
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);
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always @(posedge clk) begin
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//$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out);
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cyc <= cyc + 1;
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if (cyc == 0) begin
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// Setup
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in <= 1'b1;
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end
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else if (cyc == 1) begin
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in <= 1'b0;
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end
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else if (cyc == 2) begin
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if (out != 1'b1) $stop;
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end
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else if (cyc == 3) begin
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if (out != 1'b0) $stop;
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end
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else if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Generate (
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clk,
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value,
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result
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);
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input clk;
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input value;
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output result;
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reg Internal;
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assign result = Internal;
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always @(posedge clk) Internal <= value;
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endmodule
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module Checker (
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clk,
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value
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);
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input clk, value;
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always @(posedge clk) begin
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$write("[%0t] value=%h\n", $time, value);
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end
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endmodule
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module Test (
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clk,
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value,
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result
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);
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input clk;
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input value;
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output result;
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Generate gen (
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clk,
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value,
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result
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);
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Checker chk (
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clk,
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gen.Internal
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);
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endmodule
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module Genit (
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clk,
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value,
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result
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);
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input clk;
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input value;
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output result;
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`define WITH_GENERATE
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`ifdef WITH_GENERATE
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genvar i;
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generate
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for (genvar i = 0; i < 1; i = i + 1) begin : foo
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Test tt (
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clk,
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value,
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result
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);
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end
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endgenerate
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`else
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Test tt (
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clk,
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value,
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result
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);
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`endif
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wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
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always @(posedge clk) begin
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$write("[%0t] Result2 = %x\n", $time, Result2);
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end
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endmodule
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