Sumanth Kadiyala 44fe96b2da Add `+verilator+assert+lock` to ignore RTL assert control statements (#8086) ... Co-authored-by: Sumanth Kadiyala <sumanth@hudson-trading.com>		2026-08-12 19:13:02 -04:00
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t	Add `+verilator+assert+lock` to ignore RTL assert control statements (#8086)	2026-08-12 19:13:02 -04:00
.gdbinit	…
.gitignore	…
AGENTS.md	…
CMakeLists.txt	…
Makefile	…
Makefile_obj	…
driver.py	Tests: Add TSan and failing multi-threaded data race test (#7913)	2026-07-10 14:34:51 +01:00
input.vc	…
input.xsim.vc	…
tsan.supp	Tests: Add TSan and failing multi-threaded data race test (#7913)	2026-07-10 14:34:51 +01:00