31 lines
496 B
Systemverilog
31 lines
496 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int cyc;
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event e;
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always @(e) begin
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$display("e=%0d", e.triggered);
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->e;
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cyc = cyc + 1;
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if (cyc >= 10) begin
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$display("Fin");
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$finish;
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end
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end
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initial begin
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#1;
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->e;
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#1;
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end
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final begin
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if (cyc != 10) $stop;
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end
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endmodule
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