23 lines
440 B
Systemverilog
23 lines
440 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// The invalid break exits after LinkJump handles the shadowed disable target.
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module t;
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initial begin : blk
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fork
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join
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end
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initial fork : caller
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begin : blk
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disable t.blk;
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break;
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end
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join
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endmodule
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