87 lines
1.7 KiB
Systemverilog
87 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class ExtClkMonitor;
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bit clk;
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bit [3:0] value;
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covergroup ext_cg @(posedge clk);
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cp_val: coverpoint value {bins lo = {[0 : 7]}; bins hi = {[8 : 15]};}
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endgroup
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function new();
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ext_cg = new;
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endfunction
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endclass
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class Lvl;
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bit ev;
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endclass
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class Mid;
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Lvl lvl;
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endclass
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class ChainMonitor;
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bit a;
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Mid mid;
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bit [3:0] value;
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covergroup chain_cg @(posedge a or posedge mid.lvl.ev);
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cp_val: coverpoint value {bins lo = {[0 : 7]}; bins hi = {[8 : 15]};}
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endgroup
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function new();
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mid = new;
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mid.lvl = new;
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chain_cg = new;
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endfunction
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endclass
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module t;
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ExtClkMonitor extm;
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ChainMonitor chain;
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int i;
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initial begin
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extm = new;
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extm.value = 4'h3;
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// This edge must be sampled before the caller first blocks at #1 (IEEE 1800-2023 19.3);
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// normal fork-join_none startup deferral (IEEE 1800-2023 9.3.2) would miss it.
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extm.clk = 1'b1;
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#1;
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chain = new;
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for (i = 0; i < 8; ++i) begin
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extm.value = 4'h8 | i[3:0];
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extm.clk = 1'b0;
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#1;
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extm.clk = 1'b1;
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#1;
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end
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for (i = 0; i < 4; ++i) begin
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chain.value = 4'hc;
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chain.a = 1'b0;
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#1;
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chain.a = 1'b1;
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#1;
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end
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for (i = 0; i < 3; ++i) begin
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chain.value = 4'h2;
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chain.mid.lvl.ev = 1'b0;
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#1;
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chain.mid.lvl.ev = 1'b1;
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#1;
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end
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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