79 lines
1.6 KiB
Systemverilog
79 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class Outer;
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bit [3:0] outer_value;
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class CoverpointInner;
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bit clk;
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covergroup cg @(posedge clk);
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cp: coverpoint outer_value;
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endgroup
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function new();
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cg = new;
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endfunction
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endclass
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class IffInner;
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bit [3:0] inner_value;
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covergroup cg;
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cp: coverpoint inner_value iff (outer_value != 0);
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endgroup
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function new();
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cg = new;
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endfunction
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endclass
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endclass
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// IEEE 1800-2012 8.18 does not make local base-class members visible to subclasses,
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// even though 8.13 makes non-local inherited members part of the derived class.
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class LocalBase;
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local bit [3:0] local_value;
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endclass
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class LocalDerived extends LocalBase;
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covergroup cg;
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cp: coverpoint local_value;
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endgroup
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function new();
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cg = new;
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endfunction
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endclass
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class LocalEventBase;
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local bit local_event;
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endclass
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class LocalEventDerived extends LocalEventBase;
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covergroup cg @(posedge local_event);
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cp: coverpoint 1'b1;
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endgroup
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function new();
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cg = new;
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endfunction
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endclass
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module t;
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Outer::CoverpointInner coverpoint_inner;
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Outer::IffInner iff_inner;
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LocalDerived local_derived;
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LocalEventDerived local_event_derived;
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initial begin
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coverpoint_inner = new;
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iff_inner = new;
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local_derived = new;
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local_event_derived = new;
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end
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endmodule
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