57 lines
1.7 KiB
Systemverilog
57 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 BRDR LIFE
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// SPDX-License-Identifier: CC0-1.0
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// A 'unique' constraint takes part in constraint_mode(), and a 'unique' over a
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// typedef'd array resolves through the typedef.
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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typedef bit [1:0] arr_t[4];
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class C;
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rand arr_t arr;
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constraint uniq {unique {arr};}
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endclass
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module t;
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initial begin
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automatic C c = new;
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int ok;
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// Four distinct 2-bit values are a permutation of 0..3
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for (int i = 0; i < 10; ++i) begin
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ok = c.randomize();
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`checkd(ok, 1);
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foreach (c.arr[j]) foreach (c.arr[k]) if (j != k) `checkh(c.arr[j] == c.arr[k], 1'b0);
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end
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ok = c.randomize() with {arr[0] == arr[1];};
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`checkd(ok, 0);
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// Disabled, the array is unconstrained
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c.uniq.constraint_mode(0);
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ok = c.randomize() with {arr[0] == arr[1];};
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`checkd(ok, 1);
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// Enabled again, distinctness is back
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c.uniq.constraint_mode(1);
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ok = c.randomize() with {arr[0] == arr[1];};
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`checkd(ok, 0);
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for (int i = 0; i < 10; ++i) begin
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ok = c.randomize();
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`checkd(ok, 1);
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foreach (c.arr[j]) foreach (c.arr[k]) if (j != k) `checkh(c.arr[j] == c.arr[k], 1'b0);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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