74 lines
2.0 KiB
Systemverilog
74 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 BRDR LIFE
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// SPDX-License-Identifier: CC0-1.0
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// A 'unique' constraint holds over containers whose element count is only
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// settled at randomize() time, and over an array it constrains on its own.
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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class Sized;
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rand bit [3:0] q[$];
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rand bit [3:0] d[];
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constraint sz {
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q.size() == 3;
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d.size() == 5;
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}
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constraint uniq {
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unique {q};
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unique {d};
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}
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endclass
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class Tiny;
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rand bit [3:0] q[$];
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constraint sz {q.size() == 1;}
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constraint uniq {unique {q};}
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endclass
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class Sole;
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rand bit [1:0] arr[4];
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constraint uniq {unique {arr};}
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endclass
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module t;
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initial begin
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automatic Sized sized = new;
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automatic Tiny tiny = new;
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automatic Sole sole = new;
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int ok;
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for (int n = 0; n < 10; ++n) begin
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ok = sized.randomize();
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`checkd(ok, 1);
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`checkd(sized.q.size(), 3);
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`checkd(sized.d.size(), 5);
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foreach (sized.q[i]) foreach (sized.q[j]) if (i != j) `checkh(sized.q[i] == sized.q[j], 1'b0);
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foreach (sized.d[i]) foreach (sized.d[j]) if (i != j) `checkh(sized.d[i] == sized.d[j], 1'b0);
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// A single element is trivially unique
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ok = tiny.randomize();
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`checkd(ok, 1);
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`checkd(tiny.q.size(), 1);
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// Four distinct 2-bit values are a permutation of 0..3
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ok = sole.randomize();
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`checkd(ok, 1);
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foreach (sole.arr[i])
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foreach (sole.arr[j]) if (i != j) `checkh(sole.arr[i] == sole.arr[j], 1'b0);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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