46 lines
1.3 KiB
Systemverilog
46 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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package uvm_pkg;
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virtual class uvm_component;
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function new(string name, uvm_component parent);
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endfunction
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endclass
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class uvm_sequencer_base extends uvm_component;
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function new(string name, int parent);
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super.new(name, parent); // <- 'int' passed instead of 'uvm_component', no type error
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endfunction
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endclass
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class uvm_sequencer_param_base #(
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type REQ = int
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) extends uvm_sequencer_base;
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function new(string name, uvm_component parent);
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super.new(name, parent); // <- 'uvm_component' passed instead of 'int', no type error
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endfunction
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endclass
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class uvm_sequencer #(
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type REQ = int
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) extends uvm_sequencer_param_base #(REQ);
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function new(string name, uvm_component parent);
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super.new(name, parent);
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endfunction
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endclass
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endpackage
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package s_core_env_pkg;
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class s_core_p_base_vsequencer extends uvm_sequencer;
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function new(input string name, input uvm_component parent);
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super.new(name, parent);
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endfunction
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endclass
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endpackage
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package s_core_tests_pkg;
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import s_core_env_pkg::*;
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endpackage
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import uvm_pkg::*;
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