71 lines
2.1 KiB
Systemverilog
71 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Run with +verilator+assert+lock, which freezes the enabled assertions, so
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// every assertion control below is ignored and all directives keep firing.
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// verilog_format: off
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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// verilog_format: on
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`ifdef T_ASSERT_CTL_LOCK_ARG_NOASSERT
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`define ctl_on_off 3 // On, ignored as the assertions stay disabled
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`define expected 0
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`else
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`define ctl_on_off 4 // Off, ignored as the assertions stay enabled
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`define expected 10
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`endif
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module t;
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logic clk = 0;
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logic fals = 1'b0;
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int imm_fails = 0;
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int conc_fails = 0;
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int assume_fails = 0;
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int ctl;
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always #5 clk = ~clk;
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// posedge clk at t = 5, 15, 25, 35, 45, 55, 65, 75, 85, 95
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always @(posedge clk) imm_assert : assert (fals) else imm_fails = imm_fails + 1;
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conc_assert : assert property (@(posedge clk) fals) else conc_fails = conc_fails + 1;
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conc_assume : assume property (@(posedge clk) fals) else assume_fails = assume_fails + 1;
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initial begin
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#6; // t=6
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$assertcontrol(`ctl_on_off); // On or Off, whichever would flip all types
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#10; // t=16
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$assertcontrol(`ctl_on_off, 2); // Same, but only for SIMPLE_IMMEDIATE
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#10; // t=26
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$assertcontrol(1); // Lock
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$assertcontrol(2); // Unlock
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#10; // t=36
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$assertcontrol(5); // Kill
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#10; // t=46
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$assertpassoff;
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$assertfailoff;
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#10; // t=56
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ctl = `ctl_on_off;
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$assertcontrol(ctl); // Same again, via a non-constant control_type
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#10; // t=66
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$assertkill;
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#34; // t=100
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$finish;
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end
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// Every directive kept the enabled state it started with, as no control
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// above took effect
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final begin
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`checkd(imm_fails, `expected);
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`checkd(conc_fails, `expected);
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`checkd(assume_fails, `expected);
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$write("*-* All Finished *-*\n");
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end
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endmodule
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