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verilator/test_regress
T
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Geza Lore 745605efe3 Fix DFG removing forceable signals (#4942) 
DFG could remove forceable signals by replacing them with their
in-design driver. This is a bit of a pain to prevent, and ideally the
forcing transform should happen before DFG, but implementing it there is
a pain due to having to rewrite ports based on direction.  This is an
attempted fix in DFG. More cases might remain.
2024-03-03 16:22:41 +00:00
..
t
Fix DFG removing forceable signals (#4942)
2024-03-03 16:22:41 +00:00
.gdbinit
Revert .gdbinit modified by accident. (#4330)
2023-06-30 16:57:31 -04:00
.gitignore
Ignore some files generated by modelsim (#2669)
2020-12-05 21:55:56 -05:00
CMakeLists.txt
Copyright year update
2024-01-01 03:19:59 -05:00
driver.pl
Make installation relocatable, and the installation testable (#4927)
2024-03-01 00:08:28 +00:00
input.vc
Tests: Avoid verilated.v include in most tests
2024-02-27 18:08:37 -05:00
input.xsim.vc
Tests: Avoid verilated.v include in most tests
2024-02-27 18:08:37 -05:00
Makefile
Make installation relocatable, and the installation testable (#4927)
2024-03-01 00:08:28 +00:00
Makefile_obj
Copyright year update
2024-01-01 03:19:59 -05:00