verilator/test_regress
Wilson Snyder 3b1a7af74d Fix WIDTHEXTEND suppression on add/sub with single-bit signal. 2026-01-09 00:25:12 -05:00
..
t Fix WIDTHEXTEND suppression on add/sub with single-bit signal. 2026-01-09 00:25:12 -05:00
.gdbinit
.gitignore
CMakeLists.txt Copyright year update. 2026-01-01 07:22:09 -05:00
Makefile Copyright year update. 2026-01-01 07:22:09 -05:00
Makefile_obj Copyright year update. 2026-01-01 07:22:09 -05:00
driver.py Tests: Add self-checking tests for tagged union features (#6867 partial) (#6869) 2026-01-04 11:22:52 -04:00
input.vc
input.xsim.vc