25 lines
593 B
Systemverilog
25 lines
593 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module randcase_tb;
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int count;
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initial begin
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for (int i = 0; i < 100; i++) begin
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fork
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randcase
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1: count++;
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5: count--;
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3: ;
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endcase
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join_none
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end
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#1;
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if (count > 30) $stop; // Realistically won't happen (10^25) though not impossible
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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